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公开(公告)号:US09939839B2
公开(公告)日:2018-04-10
申请号:US14879863
申请日:2015-10-09
申请人: Ambiq Micro, Inc.
IPC分类号: G06F1/06 , H03L7/06 , H03L7/181 , H03L7/18 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G06F1/32
CPC分类号: G06F1/06 , G01R19/0084 , G05F1/56 , G05F1/575 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F11/3041 , G06F11/3414 , G06F13/102 , H02M3/158 , H02M2001/0045 , H03K17/687 , H03L7/00 , H03L7/06 , H03L7/18 , H03L7/181 , H03M1/12 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/14 , Y02D10/171
摘要: A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.
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公开(公告)号:US20170287534A1
公开(公告)日:2017-10-05
申请号:US15245016
申请日:2016-08-23
申请人: Ambiq Micro, Inc
IPC分类号: G11C7/14
摘要: A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.
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公开(公告)号:US20170248980A1
公开(公告)日:2017-08-31
申请号:US15516883
申请日:2015-09-15
申请人: Scott Hanson , Yanning Lu , Ambiq Micro, Inc.
发明人: Scott Hanson , Yanning Lu
CPC分类号: G06F1/06 , G01R19/0084 , G05F1/56 , G05F1/575 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F11/3041 , G06F11/3414 , G06F13/102 , H02M3/158 , H02M2001/0045 , H03K17/687 , H03L7/00 , H03L7/06 , H03L7/18 , H03L7/181 , H03M1/12 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/14 , Y02D10/171
摘要: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
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公开(公告)号:US20160109898A1
公开(公告)日:2016-04-21
申请号:US14855105
申请日:2015-09-15
申请人: Ambiq Micro, Inc.
CPC分类号: G06F1/06 , G01R19/0084 , G05F1/56 , G05F1/575 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F11/3041 , G06F11/3414 , G06F13/102 , H02M3/158 , H02M2001/0045 , H03K17/687 , H03L7/00 , H03L7/06 , H03L7/18 , H03L7/181 , H03M1/12 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/14 , Y02D10/171
摘要: A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.
摘要翻译: 一种用于电子系统的时钟发生器,包括诸如微控制器的集成电路。 选择性地使多个振荡器产生相应的多个振荡器信号。 对于多个时钟输出中的每一个,多路复用器响应于由时钟设备提供的相应选择信号选择振荡器信号中的相应一个。 响应于也由时钟设备提供的相应门信号,选择的振荡器信号被门控为相应的时钟信号。
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公开(公告)号:US20240354012A1
公开(公告)日:2024-10-24
申请号:US18760849
申请日:2024-07-01
申请人: Ambiq Micro, Inc.
IPC分类号: G06F3/06
CPC分类号: G06F3/0625 , G06F3/0626 , G06F3/0655 , G06F3/0673
摘要: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.
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公开(公告)号:US12045116B2
公开(公告)日:2024-07-23
申请号:US18093907
申请日:2023-01-06
申请人: Ambiq Micro, INc.
发明人: Ivan Bogue , Yousof Mortazavi , Jesse Coulon , Rajeev Srivastava
IPC分类号: G06F1/00 , G06F1/26 , G06F1/3296
CPC分类号: G06F1/3296 , G06F1/263
摘要: A system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.
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公开(公告)号:US11822364B2
公开(公告)日:2023-11-21
申请号:US16864155
申请日:2020-05-01
申请人: Ambiq Micro, Inc.
发明人: Scott McLean , Daniel Martin Cermak , Eric Jonathan Deal , Stephen James Sheafor , Donovan Scott Popps , Mark A Baur
IPC分类号: G06F1/3234 , G06F1/26 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G11C5/14
CPC分类号: G06F1/3243 , G06F1/26 , G06F1/3203 , G06F1/3237 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G11C5/147 , G11C5/148
摘要: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
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公开(公告)号:US11573624B1
公开(公告)日:2023-02-07
申请号:US17835217
申请日:2022-06-08
申请人: Ambiq Micro, Inc.
发明人: Ivan Bogue , Yousof Mortazavi , Jesse Coulon , Rajeev Srivastava
IPC分类号: G06F1/00 , G06F1/3296 , G06F1/26
摘要: In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.
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公开(公告)号:US20220130410A1
公开(公告)日:2022-04-28
申请号:US17081378
申请日:2020-10-27
申请人: Ambiq Micro, Inc.
发明人: Roger David Serwy
摘要: A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.
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公开(公告)号:US20220130405A1
公开(公告)日:2022-04-28
申请号:US17081640
申请日:2020-10-27
申请人: Ambiq Micro, Inc.
发明人: Roger David Serwy
摘要: A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.
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