公开(公告)号：US08487410B2

公开(公告)日：2013-07-16

申请号：US13085668

申请日：2011-04-13

Applicant: Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

Inventor： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L29/40

CPC classification number: H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

公开(公告)号：US08252682B2

公开(公告)日：2012-08-28

申请号：US12704695

申请日：2010-02-12

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L2224/02372

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

Abstract translation: 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

公开(公告)号：US08138076B2

公开(公告)日：2012-03-20

申请号：US12118919

申请日：2008-05-12

Applicant: Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

Inventor： Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/3141 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/513 ,  H01L29/517

Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.

Abstract translation: 提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。 通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。 如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。 形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。

公开(公告)号：US20120025234A1

公开(公告)日：2012-02-02

申请号：US13267701

申请日：2011-10-06

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

IPC: H01L33/06

CPC classification number: H01L33/22 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.

Abstract translation: 提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。 在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。 顶部接触层具有平坦的表面。 在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

公开(公告)号：US20110241061A1

公开(公告)日：2011-10-06

申请号：US12879584

申请日：2010-09-10

Applicant: Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

Inventor： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

IPC: H01L33/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

Abstract translation: 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US20110241040A1

公开(公告)日：2011-10-06

申请号：US12897124

申请日：2010-10-04

Applicant: Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

Inventor： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

IPC: H01L33/38 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract translation: 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US20110189837A1

公开(公告)日：2011-08-04

申请号：US12972184

申请日：2010-12-17

Applicant: Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

Inventor： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

IPC: H01L21/20

CPC classification number: H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02617 ,  H01L21/02664

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.

Abstract translation: 形成半导体结构的方法包括提供基板; 在衬底上形成缓冲/成核层; 在缓冲/成核层上形成III族氮化物（III族氮化物）层; 并对该III族氮化物层进行氮化。 形成III族氮化物层的步骤包括金属有机化学气相沉积。

公开(公告)号：US20100052066A1

公开(公告)日：2010-03-04

申请号：US12424153

申请日：2009-04-15

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Yung-Sheng Chiu ,  Chia-Lin Yu

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Yung-Sheng Chiu ,  Chia-Lin Yu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device and method for fabricating a semiconductor device for providing improved work function values and thermal stability is disclosed. The semiconductor device comprises a semiconductor substrate; an interfacial dielectric layer over the semiconductor substrate; a high-k gate dielectric layer over the interfacial dielectric layer; and a doped-conducting metal oxide layer over the high-k gate dielectric layer.

Abstract translation: 公开了一种用于制造用于提供改进的功函数值和热稳定性的半导体器件的半导体器件和方法。 半导体器件包括半导体衬底; 半导体衬底上的界面介电层; 界面介电层上的高k栅介质层; 以及在高k栅极电介质层上方的掺杂导电金属氧化物层。

公开(公告)号：US20100032696A1

公开(公告)日：2010-02-11

申请号：US12189635

申请日：2008-08-11

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu ,  Hung-Ta Lin

IPC: H01L33/00

CPC classification number: H01L33/22 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.

Abstract translation: 提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。 在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。 顶部接触层具有平坦的表面。 在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

公开(公告)号：US20090272975A1

公开(公告)日：2009-11-05

申请号：US12189558

申请日：2008-08-11

Applicant: Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chia-Lin Yu ,  Chen-Hua Yu

Inventor： Ding-Yuan Chen ,  Wen-Chih Chiou ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC: H01L33/00

CPC classification number: H01L33/007 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02595

Abstract: A structure and method for a light-emitting diode are presented. A preferred embodiment comprises a substrate with a conductive, poly-crystalline, silicon-containing layer over the substrate. A first contact layer is epitaxially grown, using the conductive, poly-crystalline, silicon-containing layer as a nucleation layer. An active layer is formed over the first contact layer, and a second contact layer is formed over the active layer.

Abstract translation: 提出了一种发光二极管的结构和方法。 优选的实施方案包括在衬底上具有导电的，多晶的含硅层的衬底。 使用导电多晶硅层作为成核层，外延生长第一接触层。 在第一接触层上形成有源层，并且在有源层上形成第二接触层。