公开(公告)号：US20110241061A1

公开(公告)日：2011-10-06

申请号：US12879584

申请日：2010-09-10

申请人： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

发明人： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

IPC分类号： H01L33/48

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

摘要翻译： 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US20110241040A1

公开(公告)日：2011-10-06

申请号：US12897124

申请日：2010-10-04

申请人： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

发明人： Chen-Hua YU ,  Hung-Pin CHANG ,  Yung-Chi LIN ,  Chia-Lin YU ,  Jui-Pin HUNG ,  Chien Ling HWANG

IPC分类号： H01L33/38 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

摘要翻译： 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US20100244247A1

公开(公告)日：2010-09-30

申请号：US12722949

申请日：2010-03-12

申请人： Hung-Pin CHANG ,  Wen-Chih CHIOU ,  Chen-Hua YU

发明人： Hung-Pin CHANG ,  Wen-Chih CHIOU ,  Chen-Hua YU

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

摘要： A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer.

摘要翻译： 通孔蚀刻工艺通过具有圆角和锥形侧壁轮廓形成通孔基板。 一种方法包括提供半导体衬底; 在所述半导体衬底上形成硬掩模层和图案化的光致抗蚀剂层; 在所述硬掩模中形成开口并暴露所述半导体衬底的一部分; 使用图案化的光致抗蚀剂层和硬掩模层作为掩模元件形成穿过半导体衬底的至少一部分的通孔; 执行修整过程以绕过通孔的顶角; 并除去光致抗蚀剂层。

公开(公告)号：US20130087908A1

公开(公告)日：2013-04-11

申请号：US13267200

申请日：2011-10-06

申请人： Chen-Hua YU ,  Hung-Pin CHANG ,  An-Jhih SU ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

发明人： Chen-Hua YU ,  Hung-Pin CHANG ,  An-Jhih SU ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

IPC分类号： H01L23/498

CPC分类号： H01L23/293 ,  H01L23/3192 ,  H01L24/01 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.

摘要翻译： 半导体器件包括形成在钝化后互连（PPI）线上并由保护结构包围的凸块结构。 保护结构包括聚合物层和至少一个电介质层。 电介质层可以形成在聚合物层的顶表面上，该聚合物层的下面，插入凸起结构和聚合物层之间，插入在PPI线和聚合物层之间，覆盖聚合物层的外侧壁，或 其组合。

公开(公告)号：US20110285005A1

公开(公告)日：2011-11-24

申请号：US12781960

申请日：2010-05-18

申请人： Yung-Chi LIN ,  Jing-Cheng LIN ,  Chen-Hua YU

发明人： Yung-Chi LIN ,  Jing-Cheng LIN ,  Chen-Hua YU

IPC分类号： H01L23/538

CPC分类号： H01L21/4857 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

摘要翻译： 封装系统包括设置在插入器上的第一集成电路。 所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。 第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。 第一集成电路与第一互连结构电耦合。

公开(公告)号：US20120261827A1

公开(公告)日：2012-10-18

申请号：US13085668

申请日：2011-04-13

申请人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

发明人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

摘要翻译： 半导体部件包括具有顶面的半导体基板。 开口从顶表面延伸到半导体衬底中。 开口包括内表面。 具有第一压缩应力的第一电介质衬垫设置在开口的内表面上。 具有拉伸应力的第二电介质衬垫设置在第一电介质衬垫上。 具有设置在第二电介质衬垫上的第二压缩应力的第三绝缘衬垫。 金属阻挡层设置在第三电介质衬垫上。 导电材料设置在金属阻挡层上并填充开口。

公开(公告)号：US20130147032A1

公开(公告)日：2013-06-13

申请号：US13313747

申请日：2011-12-07

申请人： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

发明人： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

摘要翻译： 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。 形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。 钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。 通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。 这种界面电阻的降低导致金属凸块的电阻降低。

公开(公告)号：US20110027944A1

公开(公告)日：2011-02-03

申请号：US12768025

申请日：2010-04-27

申请人： Chung-Shi LIU ,  Shin-Puu JENG ,  Mirng-Ji LII ,  Chen-Hua YU

发明人： Chung-Shi LIU ,  Shin-Puu JENG ,  Mirng-Ji LII ,  Chen-Hua YU

IPC分类号： H01L21/768 ,  H01L21/56

CPC分类号： H01L23/3171 ,  H01L21/563 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.

摘要翻译： 形成与半导体晶片的电连接的方法。 提供了包括绝缘层的半导体晶片。 绝缘层具有表面。 在绝缘层的表面上形成图案化掩模层。 图案化掩模层通过多个孔暴露绝缘层的表面的部分。 多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。 金属材料的细长柱具有侧壁表面。 去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。 保护层形成在金属材料的细长柱的暴露的侧壁表面上。

公开(公告)号：US20110001250A1

公开(公告)日：2011-01-06

申请号：US12825822

申请日：2010-06-29

申请人： Jing-Cheng LIN ,  Chen-Hua YU

发明人： Jing-Cheng LIN ,  Chen-Hua YU

IPC分类号： H01L23/488 ,  B05D5/12 ,  B32B3/00

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/1146

摘要： A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.

摘要翻译： 提供了一种用于金属间化合物（IMC）对Cu柱凸块的良好粘附的方法和结构。 该方法包括沉积Cu以形成Cu柱层，在Cu柱层的顶部上沉积扩散阻挡层，并在扩散阻挡层的顶部上沉积Cu覆盖层，其中形成金属间化合物（IMC） 扩散阻挡层，Cu覆盖层和位于Cu覆盖层顶部的焊料层。 IMC对Cu柱结构具有良好的粘附性，IMC的厚度可由Cu覆盖层的厚度控制，扩散阻挡层限制Cu从Cu柱层到焊料层的扩散。 该方法可以进一步包括在沉积Cu覆盖层之前在扩散阻挡层的顶部沉积薄层以获得润湿性。

公开(公告)号：US20100330788A1

公开(公告)日：2010-12-30

申请号：US12818362

申请日：2010-06-18

申请人： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO

发明人： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO

IPC分类号： H01L21/265 ,  H01L21/26 ,  H01L21/306 ,  H01L21/3205 ,  B32B7/12 ,  C23C14/34 ,  B24B1/00

CPC分类号： H01L21/187 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T428/1476

摘要： A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

摘要翻译： 薄晶片处理结构包括半导体晶片，可通过施加能量释放的释放层，可通过溶剂除去的粘合剂层和载体，其中通过涂覆或层压将剥离层施加在载体上， 通过涂布或层压将粘合剂层施加在半导体晶片上，半导体晶片和载体与剥离层和粘合剂层粘合在一起。 该方法包括在载体上施加剥离层，在半导体晶片上施加粘合剂层，粘合载体和半导体晶片，通过在释放层上施加能量来释放载体，例如， UV或激光，并且通过溶剂清洁半导体的表面以除去粘合剂层的任何残余物。