公开(公告)号：US08946742B2

公开(公告)日：2015-02-03

申请号：US12897124

申请日：2010-10-04

Applicant: Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

Inventor： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC: H01L33/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L33/48 ,  H01L33/64 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L33/62

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract translation: 具有上述通孔硅衬底（或通孔）的基板消除了对导电凸块的需要。 流程非常简单，成本效益高。 所描述的结构将单独的TSV，再分配层和导电凸块结构组合成单个结构。 通过组合单独的结构，产生具有高散热能力的低电阻电连接。 此外，具有通过硅插头（或通孔或沟槽）的基板还允许将多个芯片封装在一起。 通过硅沟槽可围绕一个或多个芯片，以在制造期间提供防止铜扩散到相邻器件的保护。 此外，具有相似或不同功能的多个芯片可以集成在TSV基板上。 通过具有不同图案的硅插头可以在半导体芯片下使用以改善散热并解决制造问题。

公开(公告)号：US08841773B2

公开(公告)日：2014-09-23

申请号：US13608456

申请日：2012-09-10

Applicant: Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract translation: 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US08507940B2

公开(公告)日：2013-08-13

申请号：US12879584

申请日：2010-09-10

Applicant: Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

Inventor： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC: H01L33/00

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

Abstract translation: 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US20110241217A1

公开(公告)日：2011-10-06

申请号：US12750100

申请日：2010-03-30

Applicant: Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract translation: 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US07541898B2

公开(公告)日：2009-06-02

申请号：US11849914

申请日：2007-09-04

Applicant: Jiangyuan Qian ,  Hung-Pin Chang ,  Bedri A. Cetiner ,  Mark Bachman ,  Franco DeFlaviis ,  Guann-Pyng Li

Inventor： Jiangyuan Qian ,  Hung-Pin Chang ,  Bedri A. Cetiner ,  Mark Bachman ,  Franco DeFlaviis ,  Guann-Pyng Li

IPC: H01P1/10 ,  B81B5/00

CPC classification number: H01H59/0009 ,  H01G5/16 ,  H01G5/40 ,  H01H2001/0084 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: The systems and methods described herein provide for a radio frequency micro-electromechanical systems switch having two or more resonant frequencies. The switch can be configured as a capacitive shunt switch having a deflectable member coupled between two electrodes over a transmission line. A first insulator can be located between one of the electrodes and the deflectable member to form a capacitive element. The deflectable member can be deflectable between an up-state and a down-state, the down-state capacitively coupling the deflectable member with the transmission line. The degree by which the deflectable member overlaps the first insulator can be adjusted to adjust the capacitance of the capacitive element and the resulting resonant frequency.

Abstract translation: 本文所述的系统和方法提供具有两个或更多个谐振频率的射频微机电系统开关。 开关可以被配置为具有通过传输线耦合在两个电极之间的可偏转构件的电容分流开关。 第一绝缘体可以位于电极之间和可偏转构件之间，以形成电容元件。 可偏转构件可以在上升状态和下降状态之间偏转，下降状态将可偏转构件与传输线电容耦合。 可以调节可偏转构件与第一绝缘体重叠的程度，以调整电容元件的电容和所得到的谐振频率。

公开(公告)号：US20050248423A1

公开(公告)日：2005-11-10

申请号：US11080112

申请日：2005-03-14

Applicant: Jiangyuan Qian ,  Hung-Pin Chang ,  Bedri Cetiner ,  Mark Bachman ,  Franco DeFlaviis ,  Guann-Pyng Li

Inventor： Jiangyuan Qian ,  Hung-Pin Chang ,  Bedri Cetiner ,  Mark Bachman ,  Franco DeFlaviis ,  Guann-Pyng Li

IPC: H01H59/00 ,  H01P1/10

CPC classification number: H01H59/0009 ,  H01G5/16 ,  H01G5/40 ,  H01H2001/0084 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: The systems and methods described herein provide for a radio frequency micro-electromechanical systems switch having two or more resonant frequencies. The switch can be configured as a capacitive shunt switch having a deflectable member coupled between two electrodes over a transmission line. A first insulator can be located between one of the electrodes and the deflectable member to form a capacitive element. The deflectable member can be deflectable between an up-state and a down-state, the down-state capacitively coupling the deflectable member with the transmission line. The degree by which the deflectable member overlaps the first insulator can be adjusted to adjust the capacitance of the capacitive element and the resulting resonant frequency.

Abstract translation: 本文所述的系统和方法提供具有两个或更多个谐振频率的射频微机电系统开关。 开关可以被配置为具有通过传输线耦合在两个电极之间的可偏转构件的电容分流开关。 第一绝缘体可以位于电极之间和可偏转构件之间，以形成电容元件。 可偏转构件可以在上升状态和下降状态之间偏转，下降状态将可偏转构件与传输线电容耦合。 可以调节可偏转构件与第一绝缘体重叠的程度，以调整电容元件的电容和所得到的谐振频率。

公开(公告)号：US08853830B2

公开(公告)日：2014-10-07

申请号：US12178021

申请日：2008-07-23

Applicant: Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/538 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

Abstract translation: 本发明提供一种制造用于半导体衬底叠层系统的半导体衬底结构的方法。 该方法包括半导体衬底，其包括前表面，背面，体层，互连层，其包括夹在导电层之间的多个金属间介电层，位于体层和互连之间的接触层 层，以及从本体层和接触层之间开始并终止于衬底背面的TSV结构。 TSV结构电耦合到互连层，并且TSV结构电耦合到背面的接合焊盘。

公开(公告)号：US08445296B2

公开(公告)日：2013-05-21

申请号：US13189287

申请日：2011-07-22

Applicant: Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

Inventor： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

IPC: H01L21/02

CPC classification number: H01J37/32963

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Abstract translation: 执行终点确定的方法和装置。 一种方法包括将晶片接收到用于进行RIE蚀刻的蚀刻工具室中; 开始RIE蚀刻以在晶片中形成通孔; 接收与RIE蚀刻工艺相关的蚀刻工具室的一个或多个物理参数的原位测量; 为腔室中的RIE蚀刻提供虚拟计量模型; 将接收到的原位测量值输入到腔室中的RIE蚀刻的虚拟测量模型; 执行虚拟计量模型以通过深度估计电流; 将经过深度的估计电流与目标深度进行比较; 并且当比较指示当前经过深度在目标深度的预定阈值内时; 输出停止信号。 公开了一种用于该方法实施例的装置。

公开(公告)号：US08319336B2

公开(公告)日：2012-11-27

申请号：US12832184

申请日：2010-07-08

Applicant: Hung-Pin Chang ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chen-Hua Yu

IPC: H01L23/34

CPC classification number: H01L33/647 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L33/642 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2933/0075 ,  H01L2924/013 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time.

Abstract translation: 上述TSV的图形（或布局）和图案密度提供可以用减少的蚀刻微载荷效应并且具有良好的管芯内均匀性而被蚀刻的TSV的布局。 不同组别的TSV（或物理上分离的组或具有不同功能的组）的TSV的模式和模式密度在不同组中应该相当接近。 不同组的TSV（或具有不同功能的TSV或物理分离的TSV组）应具有相对较近的形状，尺寸和深度，以允许所有TSV的纵横比在受控（和最佳）范围内。 应仔细选择TSV的尺寸和深度，以优化蚀刻时间和金属间隙填充时间。

公开(公告)号：US20120007132A1

公开(公告)日：2012-01-12

申请号：US12832184

申请日：2010-07-08

Applicant: Hung-Pin Chang ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chen-Hua Yu

IPC: H01L33/38 ,  H01L21/3065

CPC classification number: H01L33/647 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L33/642 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2933/0075 ,  H01L2924/013 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time.

Abstract translation: 上述TSV的图形（或布局）和图案密度提供可以用减少的蚀刻微载荷效应并且具有良好的管芯内均匀性而被蚀刻的TSV的布局。 不同组别的TSV（或物理上分离的组或具有不同功能的组）的TSV的模式和模式密度在不同组中应该相当接近。 不同组的TSV（或具有不同功能的TSV或物理分离的TSV组）应具有相对较近的形状，尺寸和深度，以允许所有TSV的纵横比在受控（和最佳）范围内。 应仔细选择TSV的尺寸和深度，以优化蚀刻时间和金属间隙填充时间。