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    HIGH EFFICIENCY LIGHT EMITTING DIODE
    13.
    发明申请
    HIGH EFFICIENCY LIGHT EMITTING DIODE 有权
    高效发光二极管

    公开(公告)号：US20110227109A1

    公开(公告)日：2011-09-22

    申请号：US12986774

    申请日：2011-01-07

    Applicant: Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM

    Inventor： Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM

    IPC: H01L33/46 ,  H01L33/38

    CPC classification number: H01L33/22 ,  H01L33/20 ,  H01L33/382

    Abstract: Provided is a high-efficiency light emitting diode (LED) that includes: a support substrate; a semiconductor stack positioned on the support substrate, the semiconductor stack including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; a first electrode positioned between the support substrate and the semiconductor stack and in ohmic contact with the semiconductor stack; a first bonding pad positioned on a portion of the first electrode that is exposed outside of the semiconductor stack; and a second electrode positioned on the semiconductor stack. Protrusions are formed on exposed surfaces of the semiconductor stack. In addition, the second electrode may be positioned between the first electrode and the support substrate and contacted with the n-type compound semiconductor layer through openings of the semiconductor stack.

    Abstract translation: 提供了一种高效率发光二极管（LED），其包括：支撑基板; 位于所述支撑基板上的半导体堆叠，所述半导体堆叠包括p型化合物半导体层，有源层和n型化合物半导体层; 位于所述支撑衬底和所述半导体堆叠之间并与所述半导体堆叠欧姆接触的第一电极; 位于所述第一电极的暴露于所述半导体叠层外部的部分上的第一焊盘; 以及位于半导体堆叠上的第二电极。 突起形成在半导体堆叠的暴露表面上。 此外，第二电极可以位于第一电极和支撑衬底之间，并且通过半导体叠层的开口与n型化合物半导体层接触。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS
    14.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS 有权
    用导电模式制作半导体器件的方法

    公开(公告)号：US20110217835A1

    公开(公告)日：2011-09-08

    申请号：US13110113

    申请日：2011-05-18

    Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

    IPC: H01L21/28

    CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

    Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

    Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

    WIDEBAND RECEIVER
    15.
    发明申请
    WIDEBAND RECEIVER 有权
    宽带接收机

    公开(公告)号：US20110135045A1

    公开(公告)日：2011-06-09

    申请号：US12970874

    申请日：2010-12-16

    Applicant: Hyun Kyu YU ,  Joon Hee Lee ,  Seong Hwan Cho

    Inventor： Hyun Kyu YU ,  Joon Hee Lee ,  Seong Hwan Cho

    IPC: H04B1/10

    CPC classification number: H04B1/28 ,  H03D7/1441 ,  H03D7/1458

    Abstract: Provided is a wideband receiver that has a smaller area and consumes less power and can prevent harmonic mixing occurring due to an increase in the number of communications systems using wideband. A wideband receiver according to an aspect of the invention may include: an front-end unit receiving and performing low-pass filtering on a wideband input signal in a continuous-time domain; and a down-conversion unit sampling and holding an output signal of the front-end unit according to a local oscillator signal and performing low-pass filtering on the output signal in a discrete tie domain.

    Abstract translation: 提供了一种宽带接收机，其具有较小的面积并且消耗更少的功率，并且可以防止由于使用宽带的通信系统的数量的增加而发生谐波混合。 根据本发明的一个方面的宽带接收机可以包括：前端单元在连续时域中接收并对宽带输入信号执行低通滤波; 下变频单元根据本地振荡器信号对前端单元的输出信号进行采样和保持，并对离散的连接域中的输出信号进行低通滤波。

    Method of applying wire voltage to semiconductor device
    16.
    发明授权
    Method of applying wire voltage to semiconductor device 有权
    将线电压施加到半导体器件的方法

    公开(公告)号：US07920021B2

    公开(公告)日：2011-04-05

    申请号：US12580299

    申请日：2009-10-16

    Applicant: Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    Inventor： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    IPC: H01L25/00

    CPC classification number: G11C16/10

    Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

    Abstract translation: 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

    METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE
    18.
    发明申请
    METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE 有权
    将电压施加到半导体器件的方法

    公开(公告)号：US20100207690A1

    公开(公告)日：2010-08-19

    申请号：US12580299

    申请日：2009-10-16

    Applicant: Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    Inventor： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    IPC: H03H11/24 ,  H03F3/14

    CPC classification number: G11C16/10

    Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

    Abstract translation: 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

    Non-volatile memory devices having floating gates
    20.
    发明授权
    Non-volatile memory devices having floating gates 失效
    具有浮动门的非易失性存储器件

    公开(公告)号：US07592665B2

    公开(公告)日：2009-09-22

    申请号：US11594327

    申请日：2006-11-08

    Applicant: Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    Inventor： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC: H01L29/788

    CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    Abstract: A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    Abstract translation: 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。

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