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    Test structure
    11.
    发明申请
    Test structure 有权
    测试结构

    公开(公告)号：US20080135840A1

    公开(公告)日：2008-06-12

    申请号：US11634588

    申请日：2006-12-06

    Applicant: Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

    Inventor： Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

    IPC: H01L23/58

    CPC classification number: H01L24/05 ,  H01L22/34 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

    Abstract translation: 用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。 测试结构在制造时被集成到半导体器件中。 金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。 大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。 待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。 导电线电耦合到相同或交替地不同金属层的测试部分。 测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

    Test chip, test board and reliability testing method
    18.
    发明授权
    Test chip, test board and reliability testing method 有权
    测试芯片，测试板和可靠性测试方法

    公开(公告)号：US09508617B2

    公开(公告)日：2016-11-29

    申请号：US13411193

    申请日：2012-03-02

    Applicant: Shiang-Ruei Su ,  Liang-Chen Lin ,  Chia-Wei Tu

    Inventor： Shiang-Ruei Su ,  Liang-Chen Lin ,  Chia-Wei Tu

    IPC: H01L21/66 ,  G01R31/28

    CPC classification number: G01R31/2856 ,  H01L21/4853 ,  H01L22/14 ,  H01L22/34 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.

    Abstract translation: 测试板包括第一芯片安装区域，第一输入区域，第二输入区域，第一输出区域和第二输出区域。 测试板还包括第一导电图案，第二导电图案，第三导电图案和第四导电图案。 第一导电图形电连接第一输入区域的第一引脚和第一芯片安装区域的第一引脚。 第二导电图形电连接第二输入区域的第一引脚和第一芯片安装区域的第二引脚。 第三导电图形电连接第一输出区域的第一引脚和第一芯片安装区域的第三引脚。 第四导电图形电连接第二输出区域的第一引脚和第一芯片安装区域的第四引脚。

    Test structure
    19.
    发明授权
    Test structure 有权
    测试结构

    公开(公告)号：US07939824B2

    公开(公告)日：2011-05-10

    申请号：US12354338

    申请日：2009-01-15

    Applicant: Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

    Inventor： Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

    IPC: H01L23/58 ,  H01L29/10

    CPC classification number: H01L24/05 ,  H01L22/34 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

    Abstract translation: 用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。 测试结构在制造时被集成到半导体器件中。 金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。 大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。 待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。 导电线电耦合到相同或交替地不同金属层的测试部分。 测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

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