公开(公告)号：US06836023B2

公开(公告)日：2004-12-28

申请号：US10413796

申请日：2003-04-14

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/492 ,  H01L24/13 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/37147 ,  H01L2224/40225 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.

Abstract translation: 公开了一种半导体管芯封装。 管芯封装包括具有第一侧和第二侧的半导体管芯，垂直晶体管和第一侧的接合焊盘。 具有第一孔的钝化层位于第一侧上，并且接合焊盘通过第一孔露出。 底涂层冶金层与钝化层直接接触。 底部基底冶金层位于第一孔内并与接合垫接触。 包含第二孔的电介质层处于与底涂层冶金层直接接触的位置。 焊料结构位于底涂层冶金层上，并且位于介电层的第二孔内。

公开(公告)号：US5789809A

公开(公告)日：1998-08-04

申请号：US517603

申请日：1995-08-22

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/12 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L23/3157 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/81801 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16152

Abstract: An integrated circuit package includes a die and an electrically conductive cap attached to the top surface of the die. The die has a top surface, a bottom surface, an edge surface, a plurality of input/output terminals on the bottom surface of the die, and an input/output terminal pad on the top surface of the die. An electrically conductive arrangement is electrically connected to the input/output terminals on the bottom surface of the die providing an arrangement for electrically connecting the input/output terminals on the bottom surface of the die to other electrical elements. The electrically conductive cap attached to the top surface of the die provides an arrangement for electrically connecting the input/output terminal on the top surface of the die to other electrical elements and may be used to provide improved heat dissipation from the die.

Abstract translation: 集成电路封装包括管芯和连接到管芯顶表面的导电帽。 模具具有顶表面，底表面，边缘表面，在模具的底表面上的多个输入/输出端子，以及在模具顶表面上的输入/输出端子垫。 导电布置电连接到管芯的底表面上的输入/输出端子，提供用于将管芯底表面上的输入/输出端子电连接到其他电气元件的装置。 连接到管芯的顶表面的导电帽提供了用于将管芯顶表面上的输入/输出端子电连接到其它电气元件的布置，并且可以用于提供来自管芯的改进的散热。

公开(公告)号：US5637916A

公开(公告)日：1997-06-10

申请号：US596434

申请日：1996-02-02

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/403 ,  Y10T29/49144 ,  Y10T29/49789 ,  Y10T29/49799

Abstract: The present invention discloses the use of a dielectric substrate panel suitable for supporting a plurality of independently packaged ICs. The substrate panel has a plurality of conductive landings arranged on its top surface, a plurality of conductive contacts arranged on its bottom surface and a multiplicity of electrically conductive vias. The vias pass through the substrate panel and are arranged to interconnect selected landings with their associated conductive contacts. The top surface of the substrate panel also includes a number of die attach areas. During packaging, dies are secured to their associated die attach areas on the substrate panel and electrically coupled to appropriate conductive landings. An encapsulant is then formed over each of the dies for protection.

Abstract translation: 本发明公开了适用于支持多个独立封装的IC的电介质基板的使用。 衬底面板具有布置在其顶表面上的多个导电平台，布置在其底表面上的多个导电触头和多个导电通孔。 通孔穿过衬底面板并且布置成将选定的平台与其相关联的导电触点相互连接。 衬底面板的顶表面还包括多个管芯附接区域。 在包装期间，管芯被固定到其相关的管芯附着区域在基板面板上并且电耦合到适当的导电平台。 然后在每个模具上形成密封剂用于保护。

公开(公告)号：US08664752B2

公开(公告)日：2014-03-04

申请号：US13430347

申请日：2012-03-26

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US20130221442A1

公开(公告)日：2013-08-29

申请号：US13406257

申请日：2012-02-27

Applicant: Rajeev JOSHI

Inventor： Rajeev JOSHI

IPC: H01L21/02 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L27/0629 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1306 ,  H05K1/186 ,  H05K3/4661 ,  H01L2924/00

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract translation: 本发明的一个方面涉及具有嵌入式功率级的集成电路封装。 集成电路封装包括彼此电耦合的第一场效应晶体管（FET）和第二FET。 FET被嵌入在由多个电介质层形成的电介质基板中。 电介质层与一个或多个箔层压在一起，这些箔层有助于形成用于封装的电互连。 各种实施例涉及形成上述包装的方法。

公开(公告)号：US08212361B2

公开(公告)日：2012-07-03

申请号：US12575641

申请日：2009-10-08

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L23/48

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US20100090331A1

公开(公告)日：2010-04-15

申请号：US12575641

申请日：2009-10-08

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US07632719B2

公开(公告)日：2009-12-15

申请号：US12350065

申请日：2009-01-07

Applicant: Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

Inventor： Seung Yong Choi ,  Min Hyo Park ,  Ji Hwan Kim ,  Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

Abstract translation: 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

公开(公告)号：US20090186452A1

公开(公告)日：2009-07-23

申请号：US12357981

申请日：2009-01-22

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC: H01L21/50

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract translation: 公开了一种用于形成螺柱凸起的半导体管芯的方法。 该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。 将形成的球按压到半导体管芯上的导电区域。 涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

公开(公告)号：US07537958B1

公开(公告)日：2009-05-26

申请号：US11283077

申请日：2005-11-18

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.