公开(公告)号：US09929264B2

公开(公告)日：2018-03-27

申请号：US15628028

申请日：2017-06-20

Applicant: United Microelectronics Corporation

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L29/417 ,  H01L21/311 ,  H01L21/768 ,  H01L29/06 ,  H01L21/225

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

公开(公告)号：US09780218B1

公开(公告)日：2017-10-03

申请号：US15144204

申请日：2016-05-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Sheng-Hsu Liu ,  Jhen-cyuan Li ,  Chih-Chung Chen ,  Man-Ling Lu ,  Chung-Min Tsai ,  Yi-wei Chen

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  Y02E10/50

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

公开(公告)号：US09768017B1

公开(公告)日：2017-09-19

申请号：US15071124

申请日：2016-03-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tsung-Hsun Tsai

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02661 ,  H01L21/02658 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66636

Abstract: The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.

公开(公告)号：US09660086B2

公开(公告)日：2017-05-23

申请号：US15156363

申请日：2016-05-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Yu Chen ,  Chung-Ting Huang ,  Ming-Hua Chang ,  Tien-Chen Chan ,  Yen-Hsing Chen ,  Hsin-Chang Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/49 ,  H01L29/51 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/26506 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

公开(公告)号：US09640663B2

公开(公告)日：2017-05-02

申请号：US14583771

申请日：2014-12-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tai-Ju Chen ,  Yi-Han Ye ,  Te-Chih Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66704 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/407 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.

公开(公告)号：US20170117380A1

公开(公告)日：2017-04-27

申请号：US14924479

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US09577029B2

公开(公告)日：2017-02-21

申请号：US14549549

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for manufacturing the same. The method includes a step hereinafter. A 5-layered dual-dielectric structure is provided on a substrate. The 5-layered dual-dielectric structure includes a bottom metal layer, a first dielectric layer, an intermediate metal layer, a second dielectric layer and a top metal layer in order. The first dielectric layer and the second dielectric layer have different thicknesses.

Abstract translation: 金属绝缘体金属（MIM）电容器结构及其制造方法。 该方法包括以下步骤。 在基板上设置5层双电介质结构。 5层双电介质结构依次包括底金属层，第一介电层，中间金属层，第二电介质层和顶金属层。 第一电介质层和第二电介质层具有不同的厚度。

公开(公告)号：US09530783B2

公开(公告)日：2016-12-27

申请号：US14729086

申请日：2015-06-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Sung-Bin Lin ,  Wen-Chung Chang

IPC: H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Abstract translation: 一种用于制造具有SONOS存储器单元的非易失性存储器的方法，其包括以下步骤：提供衬底; 在所述衬底上形成第一栅极氧化物层和第一栅极导电层; 通过在第一栅极导电层上执行光刻工艺形成MOS晶体管栅极，然后在衬底上形成ONO结构; 以及在ONO衬底上形成第二栅极导电层，然后通过在第二栅极导电层上执行光刻工艺来形成NVM晶体管栅极。

公开(公告)号：US20160329408A1

公开(公告)日：2016-11-10

申请号：US14706002

申请日：2015-05-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YEN-MING CHEN ,  CHIULING LEE ,  MIN-HSUAN TSAI ,  ZHENG HONG CHEN ,  WEI HSUAN CHANG ,  TSENG-HSUN LIU

IPC: H01L29/423

CPC classification number: H01L29/42364 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/785

Abstract: The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.

Abstract translation: 本发明提供一种晶体管，其包括具有表面的衬底; 衬底中的第一深阱区; 在衬底中的第二深阱区域，从第一深井区域隔离并环绕第一深井区域; 在衬底中和第一深阱区域上的第一阱区; 第二深井区域中的两个第二阱区域和分别在第一阱区域的两个相对侧的两个第二阱区域; 所述第一阱区域中的源极区域并且与所述表面相邻; 分别在两个第二阱区域中与表面相邻的两个漏极区域; 表面上的两个栅极结构，其中两个栅极结构中的每一个分别在源极区域和一个漏极区域之间; 以及在衬底中的围绕第二深阱区域的保护环，并且在晶体管的外围。

公开(公告)号：US20160276215A1

公开(公告)日：2016-09-22

申请号：US14660967

申请日：2015-03-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： PEI-TING LEE ,  GUO-WEI CHEN ,  CHUN-LING LIN ,  CHI-MAO HSU ,  CHING-WEI HSU ,  HUEI-RU TSAI ,  JIA-RONG LI ,  SHANG NAN CHOU ,  PO CHIH WU

IPC: H01L21/768

CPC classification number: H01L21/76862 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/18 ,  C23C28/023 ,  H01L21/28556 ,  H01L21/76849

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 在衬底上的低k电介质层中提供至少一个沟槽。 沟槽填充有铜（Cu）膜。 通过将携带Co的前体和还原剂的载气流引入到Cu膜的表面上，在Cu膜的表面上沉积纯钴（Co）。 流量的流量在5至19sccm的范围内。