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    METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER
    11.
    发明申请
    METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER 审中-公开
    使用氮化铝阻挡层制备半绝缘氮化铝的方法

    公开(公告)号：US20100109018A1

    公开(公告)日：2010-05-06

    申请号：US12610938

    申请日：2009-11-02

    Applicant: Zhen Chen ,  Umesh K. Mishra ,  Steven P. DenBaars ,  Shuji Nakamura

    Inventor： Zhen Chen ,  Umesh K. Mishra ,  Steven P. DenBaars ,  Shuji Nakamura

    IPC: H01L29/20 ,  H01L29/205 ,  H01L21/20

    CPC classification number: C30B29/406 ,  C30B25/183 ,  C30B29/36 ,  C30B29/403

    Abstract: A method for fabricating a single crystal, high quality, semi-insulating (SI) gallium nitride (GaN) layer using an AlxGa1-xN blocking layer. A buffer layer is grown on a substrate, the AlxGa1-xN blocking layer is grown on the buffer layer, and a single crystal, high quality, SI-GaN layer is grown on the AlxGa1-xN blocking layer. The AlxGa1-xN blocking layer acts as a diffusion blocking layer that prevents the diffusion of donors from the substrate from reaching the SI-GaN layer. The resulting SI-GaN layer reduces parasitic current flow and parasitic capacitive effects in electronic devices.

    Abstract translation: 使用Al x Ga 1-x N阻挡层制造单晶，高质量，半绝缘（SI）氮化镓（GaN）层的方法。 在衬底上生长缓冲层，在缓冲层上生长Al x Ga 1-x N阻挡层，并且在Al x Ga 1-x N阻挡层上生长单晶，高质量的SI-GaN层。 Al x Ga 1-x N阻挡层充当扩散阻挡层，防止供体从衬底扩散到达SI-GaN层。 所产生的SI-GaN层减少了电子器件中的寄生电流和寄生电容效应。

    METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL
    12.
    发明申请
    METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL 审中-公开
    使用波形焊接和基板去除在III面形成的层的N面上制造III-N半导体器件的方法

    公开(公告)号：US20090085065A1

    公开(公告)日：2009-04-02

    申请号：US12059907

    申请日：2008-03-31

    Applicant: Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

    Inventor： Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

    IPC: H01L29/778 ,  H01L21/18 ,  H01L21/20

    CPC classification number: H01L29/66462 ,  H01L21/187 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/7783

    Abstract: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.

    Abstract translation: 一种用于在层的N面上制造III-N半导体器件的方法，包括（a）在衬底上生长Ga极性方向上的III族氮化物半导体器件结构，（b）将III族氮化物的Ga面 半导体器件结构，以及（c）去除衬底以露出III族氮化物半导体器件结构的N面。 还公开了一种N极（000-1）取向的III族氮化物半导体器件，其包括一个或多个（000-1）取向的氮化物层，每个具有与III族面相反的N面，其中至少一个N 表面是至少部分暴露的N面，以及附着到III组面中的一个的主体衬底。

    DUAL SURFACE-ROUGHENED N-FACE HIGH-BRIGHTNESS LED
    13.
    发明申请
    DUAL SURFACE-ROUGHENED N-FACE HIGH-BRIGHTNESS LED 审中-公开
    双表面粗糙N面高亮度LED

    公开(公告)号：US20080277682A1

    公开(公告)日：2008-11-13

    申请号：US12059918

    申请日：2008-03-31

    Applicant: Umesh K. Mishra ,  Michael Grundmann ,  Steven P. DenBaars ,  Shuji Nakamura

    Inventor： Umesh K. Mishra ,  Michael Grundmann ,  Steven P. DenBaars ,  Shuji Nakamura

    IPC: H01L33/00 ,  H01L21/00

    CPC classification number: H01L33/22 ,  H01L33/04 ,  H01L33/32

    Abstract: A light emitting diode, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer and between an n-type layer and a p-type layer, a tunnel junction adjacent the p-type layer, and n-type contacts to the tunnel junction and the n-type layer, wherein the buffer layer, n-type layer, p-type layer, active region and tunnel junction comprise III-nitride material grown in a nitrogen-face (N-face) orientation. The substrate surface upon which the III-nitride material is deposited is patterned to provide embedded backside roughening. A top surface of the tunnel junction, which also the top surface of the III-nitride material, is roughened.

    Abstract translation: 一种发光二极管，包括衬底，衬底上的缓冲层，缓冲层上的有源层，n型层和p型层之间，邻近p型层的隧道结，以及n型层， 类型接触到隧道结和n型层，其中缓冲层，n型层，p型层，有源区和隧道结包括以氮面（N面）取向生长的III族氮化物材料 。 图案化其上沉积有III族氮化物材料的衬底表面以提供嵌入式背面粗糙化。 隧道结的顶表面也是III族氮化物材料的顶表面被粗糙化。

    High current, high voltage breakdown field effect transistor
    16.
    发明授权
    High current, high voltage breakdown field effect transistor 失效
    大电流，高压击穿场效应晶体管

    公开(公告)号：US5084743A

    公开(公告)日：1992-01-28

    申请号：US494239

    申请日：1990-03-15

    Applicant: Umesh K. Mishra ,  Robert J. Trew

    Inventor： Umesh K. Mishra ,  Robert J. Trew

    IPC: H01L29/43 ,  H01L29/778 ,  H01L29/812

    CPC classification number: H01L29/7783 ,  H01L29/432 ,  H01L29/812

    Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, especially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resisitivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.

    Abstract translation: 集成电路场效应晶体管，特别是化合物半导体金属半导体场效应晶体管（MESFET）和高电子迁移率晶体管（HEMT）的栅极电压击穿通过在器件的表面上形成电子俘获层而显着增加， 栅极接触并延伸超过栅极接触到漏极接触。 电子捕获层优选是具有至少1018个陷阱/立方厘米的高电阻率晶格匹配单晶层。 对于基于砷化镓的晶体管，优选通过镓和砷通量的低温分子束外延（MBE）形成电子陷阱层，以产生具有1％过量砷的单晶砷化镓层。 对于基于磷化铟的晶体管，电子捕获层优选由铝，铟和砷通量的低温MBE形成，以产生具有1％过量砷的单晶铝砷化铟层。

    Microelectronic electron emitter
    17.
    发明授权
    Microelectronic electron emitter 失效
    微电子发射体

    公开(公告)号：US5077597A

    公开(公告)日：1991-12-31

    申请号：US568901

    申请日：1990-08-17

    Applicant: Umesh K. Mishra

    Inventor： Umesh K. Mishra

    IPC: H01J1/308

    CPC classification number: B82Y15/00 ,  H01J1/308

    Abstract: A planar doped barrier region of semiconductor material is coupled to a vacuum or gaseous region to provide electron emission from the planar doped barrier region into the vacuum or gaseous region. When a voltage is applied across the planar doped barrier region electrons flow from one end of the region to another. This flow results in the emission of electrons if the work function of the emission surface is less than the bandgap of the semiconductor material. The device of the present invention can be used as a vacuum microelectronic emitter, a vacuum microelectronic transistor, light source, klystron, or travelling wave tube.

    Abstract translation: 半导体材料的平面掺杂阻挡区域耦合到真空或气体区域以提供从平面掺杂阻挡区域进入真空或气态区域的电子发射。 当跨平面掺杂阻挡区域施加电压时，电子从该区域的一端流向另一端。 如果发射表面的功函数小于半导体材料的带隙，则该流动导致电子的发射。 本发明的器件可以用作真空微电子发射器，真空微电子晶体管，光源，速调管或行波管。

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