公开(公告)号：US08643024B2

公开(公告)日：2014-02-04

申请号：US13331973

申请日：2011-12-20

Applicant: Arpan Chakraborty ,  Kwang-Choong Kim ,  James S. Speck ,  Steven P. DenBaars ,  Umesh K. Mishra

Inventor： Arpan Chakraborty ,  Kwang-Choong Kim ,  James S. Speck ,  Steven P. DenBaars ,  Umesh K. Mishra

IPC: H01L29/20

CPC classification number: H01L21/02639 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02516 ,  H01L21/0254 ,  H01L33/007

Abstract: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.

Abstract translation: 公开了一种用于生长减少缺陷密度的平面氮化镓（GaN）膜的方法。 该方法包括以下步骤：（a）在GaN模板上生长至少一个氮化硅（SiNx）纳米掩模层，和（b）在SiNx纳米掩模层的顶部生长GaN膜的厚度。

公开(公告)号：US20130264540A1

公开(公告)日：2013-10-10

申请号：US13909775

申请日：2013-06-04

Applicant: Arpan Chakraborty ,  Benjamin A. Haskell ,  Stacia Keller ,  James S. Speck ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Arpan Chakraborty ,  Benjamin A. Haskell ,  Stacia Keller ,  James S. Speck ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L33/06

CPC classification number: H01L33/06 ,  B82Y20/00 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0075 ,  H01S5/0213 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04 ,  H01S2304/12

Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.

Abstract translation: 制造非极性铟镓氮（InGaN）膜以及使用金属有机化学气相沉积（MOVCD）的非极性含InGaN的器件结构的方法。 该方法用于制造非极性InGaN / GaN紫外线和近紫外发光二极管和激光二极管。

公开(公告)号：US08334151B2

公开(公告)日：2012-12-18

申请号：US12752977

申请日：2010-04-01

Applicant: Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L21/00

CPC classification number: H01L33/22 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/32 ,  H01S5/0215 ,  H01S5/0421 ,  H01S5/18347 ,  H01S5/18369 ,  H01S5/1838 ,  H01S5/32341

Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Abstract translation: An（Al，Ga，In）N和ZnO直接晶圆键合发光二极管（LED），其中光通过导电ZnO。 为（Al，Ga，In）N和ZnO晶圆制备平坦且干净的表面。 然后在（Al，Ga，In）N和ZnO晶片之间进行晶片接合工艺，其中（Al，Ga，In）N和ZnO晶片被接合在一起，然后在氮气氛下在单轴压力下在 设定温度一段时间。 在晶片接合工艺之后，ZnO被成形为用于从LED内部增加光提取。

公开(公告)号：US20120205623A1

公开(公告)日：2012-08-16

申请号：US13457032

申请日：2012-04-26

Applicant: Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L33/06 ,  H01L33/32 ,  H01L29/201

CPC classification number: C30B29/403 ,  C30B25/02 ,  C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/406 ,  C30B29/605 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (11 02) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract translation: 一种形成非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的方法。 使用MOCVD在非平面（1120）蓝宝石衬底上生长非极性（11 20）a面GaN层。 这些非极性（11 20）a面GaN层包括用于产生非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的模板。

公开(公告)号：US20120104411A1

公开(公告)日：2012-05-03

申请号：US13283211

申请日：2011-10-27

Applicant: Michael Iza ,  Carl J. Neufeld ,  Samantha C. Cruz ,  Robert M. Farrell ,  James S. Speck ,  Shuji Nakamura ,  Steven P. DenBaars ,  Umesh K. Mishra

Inventor： Michael Iza ,  Carl J. Neufeld ,  Samantha C. Cruz ,  Robert M. Farrell ,  James S. Speck ,  Shuji Nakamura ,  Steven P. DenBaars ,  Umesh K. Mishra

IPC: H01L31/0236 ,  H01L31/18 ,  H01L31/0352 ,  H01L31/0304 ,  H01L33/32 ,  H01L33/58 ,  H01L33/22

CPC classification number: H01L33/22 ,  H01L31/02363 ,  H01L31/1856 ,  H01L33/007 ,  Y02E10/544 ,  Y02P70/521

Abstract: A method for fabricating a III-nitride semiconductor film, comprising depositing or growing a III-nitride semiconductor film in a semiconductor light absorbing or light emitting device structure; and growing a textured or structured surface of the III-nitride nitride semiconductor film in situ with the growing or the deposition of the III-nitride semiconductor film, by controlling the growing of the III-nitride semiconductor film to obtain a texture of the textured surface, or one or more structures of the structured surface, that increase output power of light from the light emitting device, or increase absorption of light in the light absorbing device.

Abstract translation: 一种制造III族氮化物半导体膜的方法，包括在半导体光吸收或发光器件结构中沉积或生长III族氮化物半导体膜; 并且通过控制III族氮化物半导体膜的生长以获得纹理表面的纹理，随着III族氮化物半导体膜的生长或沉积而原位生长III-氮化物氮化物半导体膜的织构或结构化表面 ，或结构化表面的一个或多个结构，其增加来自发光器件的光的输出功率，或增加光吸收装置中的光的吸收。

公开(公告)号：US20110204329A1

公开(公告)日：2011-08-25

申请号：US13099834

申请日：2011-05-03

Applicant: Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James Stephen Speck ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L29/15

CPC classification number: C30B29/403 ,  C30B25/02 ,  C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/406 ,  C30B29/605 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract translation: 一种形成非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的方法。 使用MOCVD在非平面（1120）蓝宝石衬底上生长非极性（11 20）a面GaN层。 这些非极性（11 20）a面GaN层包括用于产生非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的模板。

公开(公告)号：US20110156572A1

公开(公告)日：2011-06-30

申请号：US13045148

申请日：2011-03-10

Applicant: Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62 ,  H01J9/00

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US07935985B2

公开(公告)日：2011-05-03

申请号：US12059902

申请日：2008-03-31

Applicant: Umesh K. Mishra ,  Yi Pei ,  Siddharth Rajan ,  Man Hoi Wong

Inventor： Umesh K. Mishra ,  Yi Pei ,  Siddharth Rajan ,  Man Hoi Wong

IPC: H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02516 ,  H01L21/0254 ,  H01L29/0891 ,  H01L29/1608 ,  H01L29/2003

Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.

Abstract translation: 一种用于制造具有低缓冲器泄漏的氮面（N面）氮化物基电子器件的方法，包括用AlGaInN成核层从衬底隔离缓冲器以抑制从衬底掺入缓冲器中的杂质。 还公开了一种用于制造具有低寄生电阻和高击穿的N面氮化物基电子器件的方法，其包括用导电层封装器件结构以提供极低的访问和/或接触电阻。

公开(公告)号：US07911126B2

公开(公告)日：2011-03-22

申请号：US12419788

申请日：2009-04-07

Applicant: Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US20100224860A1

公开(公告)日：2010-09-09

申请号：US12782107

申请日：2010-05-18

Applicant: James P. IBBETSON ,  Bernd P. Keller ,  Umesh K. Mishra

Inventor： James P. IBBETSON ,  Bernd P. Keller ,  Umesh K. Mishra

IPC: H01L33/02 ,  H01L33/00 ,  H01L29/20 ,  H01L33/30

CPC classification number: H01L33/04 ,  H01L33/0016 ,  H01L33/08 ,  H01L33/32

Abstract: An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.

Abstract translation: 公开了一种由宽带隙半导体材料制成的LED，并具有在宽带隙半导体器件中具有隧道结的低电阻p型约束层。 不同的材料放置在材料产生天然偶极子的隧道结处。 该天然偶极子用于形成隧道宽度小于不具有不同材料的宽度的接合点。 在宽带隙半导体器件中具有隧道结的低电阻p型限制层可以通过在限制层的接合处产生极化电荷并在接合部中形成小于宽度的隧道宽度来制造 没有极化电荷。 可以通过在连接处添加杂质来增强通过限制层中的隧道结的隧穿。 这些杂质可能在结中形成带隙状态。