公开(公告)号：US08421179B2

公开(公告)日：2013-04-16

申请号：US13186494

申请日：2011-07-20

申请人： Chiun-Yen Tung ,  Kun-Hsien Chen ,  Kai-Ying Wang ,  Wen-Li Tsai

发明人： Chiun-Yen Tung ,  Kun-Hsien Chen ,  Kai-Ying Wang ,  Wen-Li Tsai

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/8611

摘要： A Schottky diode with high antistatic capability has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N− type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.

摘要翻译： 具有高抗静电能力的肖特基二极管具有形成在N +型掺杂层上的N型掺杂漂移层。 N型掺杂漂移层具有形成有保护环的表面。 保护环内部是P型掺杂区域。 N型掺杂漂移层表面还形成有氧化物层和金属层。 金属层和N型掺杂漂移层和P型掺杂区域之间的接触区域形成肖特基接触。 P型掺杂区域具有低浓度下层和高浓度上层，使得P型掺杂区域中的表面离子浓度高。 因此，肖特基二极管具有降低正向压降和高抗静电能力的优点。

公开(公告)号：US07919384B2

公开(公告)日：2011-04-05

申请号：US12050649

申请日：2008-03-18

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/20

CPC分类号： H01L28/91

摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

摘要翻译： 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20090317982A1

公开(公告)日：2009-12-24

申请号：US12142414

申请日：2008-06-19

申请人： Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

发明人： Ming Yen Li ,  Hsiao Che Wu ,  De Long Chen ,  Wen Li Tsai

IPC分类号： H01L21/31 ,  C23C16/00

CPC分类号： H01L21/0228 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45544 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/31604

摘要： An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber.

摘要翻译： 原子层沉积装置包括反应室，被配置为加热位于加热器上的半导体晶片的加热器，被配置为将具有不同氧化剂浓度的含氧化剂的前体输送到反应室的氧化剂供应源，以及被配置为输送 含金属的前体到反应室。 本申请还公开了一种制备电介质结构的方法，包括以下步骤：将基底放置在反应室中，执行第一原子层沉积工艺，包括进料含氧化剂浓度较低的含氧化剂的前体和含金属的前体 在衬底上形成较薄的界面层，并且执行第二原子层沉积工艺，包括将氧化剂浓度高于用于将第一金属氧化物层和含金属的前体生长的氧化剂浓度进料到反应室中 。

公开(公告)号：US20090189246A1

公开(公告)日：2009-07-30

申请号：US12178154

申请日：2008-07-23

申请人： Hsiao-Che WU ,  Ming-Yen LI ,  Wen-Li TSAI

发明人： Hsiao-Che WU ,  Ming-Yen LI ,  Wen-Li TSAI

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76224

摘要： A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d′ to cover and completely seal the surface of the oxide layer, wherein d′

摘要翻译： 提供了一种用于形成沟槽隔离结构和半导体器件的方法。 该方法包括以下步骤：在半导体衬底上形成图案化掩模; 通过使用图案化掩模来限定具有预定深度D的沟槽，其中沟槽具有底部和侧壁; 形成覆盖所述沟槽的底部和侧壁的衬里层; 用从底部到厚度d1的可流动氧化物基本上填充沟槽以形成氧化物层; 形成厚度d'的阻挡层以覆盖并完全密封氧化物层的表面，其中d'

公开(公告)号：US20080128892A1

公开(公告)日：2008-06-05

申请号：US11566160

申请日：2006-12-01

申请人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

发明人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

摘要翻译： 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US07781830B2

公开(公告)日：2010-08-24

申请号：US12174110

申请日：2008-07-16

申请人： Hsiao Che Wu ,  Ming Yen Li ,  Wen Li Tsai ,  Bin Siang Tsai

发明人： Hsiao Che Wu ,  Ming Yen Li ,  Wen Li Tsai ,  Bin Siang Tsai

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

摘要： A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

摘要翻译： 凹陷沟道晶体管包括具有沟槽隔离结构的半导体衬底，在半导体衬底中具有下部块的栅极结构和位于半导体衬底上的上部块，位于上部块的两侧和下部块上方的两个掺杂区域 以及位于上块的侧壁处并且具有夹在上块和掺杂区之间的底端的绝缘垫片。 特别地，两个掺杂区域分别用作源极和漏极区，并且栅极结构的下部块用作凹陷沟道晶体管的凹入栅极。

公开(公告)号：US20090061635A1

公开(公告)日：2009-03-05

申请号：US12108285

申请日：2008-04-23

申请人： Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/311

CPC分类号： H01L21/0337

摘要： A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.

摘要翻译： 公开了一种形成微图案的方法。 该方法形成牺牲层和掩模层。 在牺牲层中形成多个第一锥形沟槽。 在多个第一锥形沟槽中填充光致抗蚀剂层。 光致抗蚀剂层用作掩模，并且在牺牲层中形成多个第二锥形沟槽。 然后，剥离光致抗蚀剂层以能够通过第一锥形沟槽和牺牲层中的第二锥形沟槽图案化层。 因此，形成通过双蚀刻复制线密度的图案化牺牲层。

公开(公告)号：US20090023264A1

公开(公告)日：2009-01-22

申请号：US12050649

申请日：2008-03-18

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/02

CPC分类号： H01L28/91

摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

摘要翻译： 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20080132053A1

公开(公告)日：2008-06-05

申请号：US11566166

申请日：2006-12-01

申请人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

发明人： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/522 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/0476 ,  H01L2924/0479 ,  H01L2924/0475 ,  H01L2924/0474 ,  H01L2924/0483 ,  H01L2924/0496 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/048

摘要： An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

摘要翻译： 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US20080102207A1

公开(公告)日：2008-05-01

申请号：US11715619

申请日：2007-03-08

申请人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

发明人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

IPC分类号： C23C16/00 ,  F16K21/00

CPC分类号： C23C16/45565 ,  C23C16/45572 ,  C23C16/481 ,  H01L21/67109 ,  H01L21/67115 ,  Y10T137/9464

摘要： A gas delivering system for an in situ thermal treatment, a thin film deposition and a use of the same are provided. The gas delivering system integrates a thermal treatment system therein so that a thin film deposition and a by rapid thermal annealing can be performed alternatively on a wafer in a reaction chamber. Accordingly, the density of the thin film can be improved and the thermal budget of the process can be reduced.

摘要翻译： 提供了一种用于原位热处理，薄膜沉积及其使用的气体输送系统。 气体输送系统将其中的热处理系统集成在一起，可以在反应室中的晶片上交替地进行薄膜沉积和快速热退火。 因此，可以提高薄膜的密度，并且可以降低该方法的热预算。