公开(公告)号：US20150372118A1

公开(公告)日：2015-12-24

申请号：US14320559

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/06

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the substrate further comprising a patterned hardmask layer disposed on the multi-material layer, etching the multi-material layer through openings defined by the patterned hardmask layer to expose sidewalls of the first and the second layer of the multi-material layer, and laterally and selectively etching the second layer from the substrate.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实施方案中，在衬底上形成纳米线结构的方法包括在衬底上形成多材料层，其中所述多材料层包括第一层和第二层的重复对，所述衬底还包括图案化硬掩模层 设置在多材料层上，通过由图案化的硬掩模层限定的开口蚀刻多材料层，以暴露多材料层的第一和第二层的侧壁，并横向和选择性地从衬底上蚀刻第二层 。

公开(公告)号：US20150371852A1

公开(公告)日：2015-12-24

申请号：US14730194

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

Abstract translation: 本公开提供形成具有尺寸在14纳米以下的特征的精确尺寸控制和最小光刻相关误差的纳米结构。 本文提供了自对准多间隔图案（SAMSP）工艺，并且该工艺利用最小光刻曝光工艺，而是采用多次沉积/蚀刻工艺来逐渐减小沿制造工艺在掩模中形成的特征尺寸，直到期望的极小尺寸 在掩模层中形成纳米结构。

公开(公告)号：US20150140787A1

公开(公告)日：2015-05-21

申请号：US14548044

申请日：2014-11-19

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 在基板上执行各种处理步骤，以提供限定心轴结构的沟槽。 心轴结构的侧壁和沟槽的底表面被氧化并随后被蚀刻以减小心轴结构的宽度。 可以重复心轴结构的氧化和蚀刻，直到实现心轴结构的期望宽度。 随后将半导体材料沉积在心轴结构的再生长区域上以形成翅片结构。 氧化和蚀刻心轴结构提供了一种用于形成翅片结构的方法，其可实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US20180211881A1

公开(公告)日：2018-07-26

申请号：US15811188

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Schubert S. CHU ,  Xinyu BAO ,  Regina Germanie FREED ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

公开(公告)号：US20170092494A1

公开(公告)日：2017-03-30

申请号：US15377629

申请日：2016-12-13

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

公开(公告)号：US20160293437A1

公开(公告)日：2016-10-06

申请号：US14968500

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。

公开(公告)号：US20150099347A1

公开(公告)日：2015-04-09

申请号：US14045467

申请日：2013-10-03

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/66

CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US20190181246A1

公开(公告)日：2019-06-13

申请号：US16277634

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Ying ZHANG ,  Qingjun ZHOU ,  Yung-chen LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.

公开(公告)号：US20170194430A1

公开(公告)日：2017-07-06

申请号：US15395928

申请日：2016-12-30

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Michael G. WARD ,  Shiyu SUN ,  Michael CHUDZIK ,  Nam Sung KIM ,  Hua CHUNG ,  Yi-Chiau HUANG ,  Chentsau YING ,  Ying ZHANG ,  Chi-Nung NI ,  Lin DONG ,  Dongqing YANG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/764 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

公开(公告)号：US20160013273A1

公开(公告)日：2016-01-14

申请号：US14673033

申请日：2015-03-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L29/1037 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 可以在衬底上执行各种处理步骤，以提供在其上共形沉积介电层的沟槽。 随后在沟槽内蚀刻电介质层以暴露下面的衬底，并且半导体材料沉积在沟槽中以形成鳍结构。 形成沟槽，沉积介电层和形成鳍结构的工艺可以实现10nm以下的节点尺寸并提供越来越小的FinFET。