公开(公告)号：US08134239B2

公开(公告)日：2012-03-13

申请号：US12239900

申请日：2008-09-29

申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

公开(公告)号：US08064236B2

公开(公告)日：2011-11-22

申请号：US12477501

申请日：2009-06-03

申请人： Yoji Nishio ,  Atsushi Hiraishi

发明人： Yoji Nishio ,  Atsushi Hiraishi

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  G06F13/4072 ,  G06F13/4086 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.

摘要翻译： 在具有数据输入/输出焊盘13的终端电阻的多级存储器模块和输入控制端子电阻的接通/断开的信号的端子电阻控制焊盘14的情况下，可以借助于高速操作 即使在排列数大于设置在存储器模块上的端子电阻控制端子（ODT端子）的数量的情况下，也可以是封闭的端子电阻。 为此，在模块基板8上的数据总线19与数据输入/输出焊盘13之间具有较长互连长度的存储芯片12的端子电阻控制焊盘14连接到终端电阻控制互连 18或21以控制来自ODT端子的端子电阻的开/关。 在模块基板上的数据总线19与数据输入/输出焊盘13之间的互连的较短长度的存储芯片11上的端子电阻控制焊盘连接到固定电位20以接通端子电阻。

公开(公告)号：US20090140766A1

公开(公告)日：2009-06-04

申请号：US12292664

申请日：2008-11-24

申请人： Atsushi Hiraishi ,  Toshio Sugano

发明人： Atsushi Hiraishi ,  Toshio Sugano

IPC分类号： H03H7/40 ,  H03K19/003

CPC分类号： H05K1/0268 ,  G11C7/04 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit.

摘要翻译： 一种信号传输电路，包括：彼此连接的第一和第二传输线; 存储第一传输线的阻抗的第一阻抗存储电路; 以及控制电路，其输出第二传输线的阻抗和存储在第一阻抗存储电路中的阻抗之间的匹配信息。

公开(公告)号：US20080203584A1

公开(公告)日：2008-08-28

申请号：US12081264

申请日：2008-04-14

申请人： Mitsuaki Katagiri ,  Atsushi Hiraishi ,  Fumiyuki Osanai

发明人： Mitsuaki Katagiri ,  Atsushi Hiraishi ,  Fumiyuki Osanai

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/50 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.

摘要翻译： 与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。 允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

公开(公告)号：US20070273021A1

公开(公告)日：2007-11-29

申请号：US11802888

申请日：2007-05-25

申请人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

发明人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

IPC分类号： H01L23/12

CPC分类号： H01L23/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

公开(公告)号：US5854562A

公开(公告)日：1998-12-29

申请号：US842536

申请日：1997-04-15

申请人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

发明人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

公开(公告)号：US5700704A

公开(公告)日：1997-12-23

申请号：US458615

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

摘要翻译： 提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。 特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻 的多晶硅膜。 通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

公开(公告)号：US5652457A

公开(公告)日：1997-07-29

申请号：US351173

申请日：1994-11-30

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5398318A

公开(公告)日：1995-03-14

申请号：US608370

申请日：1990-11-02

申请人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

发明人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

IPC分类号： G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/088 ,  H03K19/0944 ,  G06F13/00

CPC分类号： H03K19/09448 ,  H03K17/164 ,  H03K19/00361

摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

摘要翻译： 提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。 缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。 这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。 例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。 电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

公开(公告)号：US5057894A

公开(公告)日：1991-10-15

申请号：US526696

申请日：1990-05-23

申请人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

发明人： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

IPC分类号： H01L21/285 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L27/0623 ,  H01L21/28525 ,  H01L21/8249

摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

摘要翻译： 公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。