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    Stacked semiconductor module
    11.
    再颁专利
    Stacked semiconductor module 有权
    堆叠式半导体模块

    公开(公告)号：USRE44019E1

    公开(公告)日：2013-02-19

    申请号：US12605303

    申请日：2009-10-23

    申请人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    发明人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    IPC分类号： H01L21/00

    CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C29/08 ,  G11C2029/4402 ,  H01L23/5382 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

    摘要翻译： 提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。 半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。 可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。 此外，提供了一种用于访问半导体模块的方法。 提供上述壳体以包围多个集成电路芯片和可编程存储器件。 然后识别满足预定标准的多个集成电路芯片的集成电路芯片。 随后编程可编程存储器件以识别所选择的集成电路芯片。

    Stacked semiconductor module
    12.
    发明授权
    Stacked semiconductor module 有权
    堆叠式半导体模块

    公开(公告)号：US06720643B1

    公开(公告)日：2004-04-13

    申请号：US09792788

    申请日：2001-02-22

    申请人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    发明人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

    IPC分类号： H01L2302

    CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C29/08 ,  G11C2029/4402 ,  H01L23/5382 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.

    摘要翻译： 提供了半导体模块，其包括半导体壳体和位于壳体内的多个集成电路模具。 该半导体模块还包括位于壳体内并可电耦合到多个集成电路管芯的可编程存储器件。 可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路管芯。 此外，提供了一种用于访问半导体模块的方法。 提供上述壳体以封闭多个集成电路管芯和可编程存储器件。 然后识别满足预定标准的多个集成电路管芯的集成电路管芯。 随后编程可编程存储器件以识别所选择的集成电路管芯。

    Clock Routing in Mulitiple Channel Modules and Bus Systems
    13.
    发明申请
    Clock Routing in Mulitiple Channel Modules and Bus Systems 审中-公开
    多通道模块和总线系统中的时钟路由

    公开(公告)号：US20120001670A1

    公开(公告)日：2012-01-05

    申请号：US13235251

    申请日：2011-09-16

    申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： G06F1/04

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

    摘要翻译： 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板。

    Clock routing in multiple channel modules and bus systems
    15.
    发明授权
    Clock routing in multiple channel modules and bus systems 失效
    多通道模块和总线系统中的时钟路由

    公开(公告)号：US06590781B2

    公开(公告)日：2003-07-08

    申请号：US09817828

    申请日：2001-03-26

    申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

    IPC分类号： H05K702

    CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

    摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

    摘要翻译： 提供了一种装置，其包括存储器接口电路，时钟信号发生电路和多个存储器电路。 存储器电路被可操作地耦合并按照多个存储器模块的顺序排列，使得位于该命令开始处的存储器模块被耦合到时钟信号发生电路和存储器接口电路的输出端。 定位在订单结尾的存储器模块是唯一的，因为它包括连接到最后存储器集成电路的时钟信号终端电路。 利用这种配置，通过将时钟信号发生电路的输出的时钟信号通过每个存储器模块以顺序（不连接到任何中间存储器集成电路）直​​接路由到存储器集成电路而形成时钟环路 定位在订单结束。 然后，时钟信号在先前的存储器模块上通过其上的存储器集成电路将其重新布置，以与定位在订单开始处的存储器集成电路相反，并且从那里到存储器接口电路。 为了完成时钟环路，时钟信号通过将存储器接口电路从存储器集成电路重新路由到存储器集成电路定位在订单结束处而被再次断言。 最后，时钟信号终止在位于订单结束的存储器模块上的时钟信号终端电路。

    Interconnection elements with encased interconnects
    17.
    发明授权
    Interconnection elements with encased interconnects 有权
    具有封装互连的互连元件

    公开(公告)号：US08988895B2

    公开(公告)日：2015-03-24

    申请号：US13215725

    申请日：2011-08-23

    申请人： Ilyas Mohammed ,  Belgacem Haba

    发明人： Ilyas Mohammed ,  Belgacem Haba

    IPC分类号： H05K7/04 ,  H01B7/00 ,  H01R43/00 ,  H01L21/50 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01R12/52

    CPC分类号： H05K3/4602 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/523 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y10T29/49176

    摘要： An interconnection element is disclosed that includes a plurality of drawn metal conductors, a dielectric layer, and opposed surfaces having a plurality of wettable contacts thereon. The conductors may include grains having lengths oriented in a direction between the first and second ends of the conductors. A dielectric layer for insulating the conductors may have first and second opposed surfaces and a thickness less than 1 millimeter between the first and second surface. One or more conductors may be configured to carry a signal to or from a microelectronic element. First and second wettable contacts may be used to bond the interconnection element to at least one of a microelectronic element and a circuit panel. The wettable contacts may match a spatial distribution of element contacts at a face of a microelectronic element or of circuit contacts exposed at a face of component other than the microelectronic element.

    摘要翻译： 公开了一种互连元件，其包括多个拉制的金属导体，电介质层和在其上具有多个可湿接触点的相对表面。 导体可以包括具有沿导体的第一和第二端之间的方向定向的长度的晶粒。 用于绝缘导体的电介质层可以具有第一和第二相对表面，并且在第一和第二表面之间可以具有小于1毫米的厚度。 一个或多个导体可以被配置为将信号传送到微电子元件或从微电子元件传送信号。 可以使用第一和第二可湿触点将互连元件接合到微电子元件和电路板中的至少一个。 可湿性触点可以匹配微电子元件的表面处的元件触点的空间分布或暴露在微电子元件以外的部件的表面处的电路触点。

    BSI image sensor package with variable-height silicon for even reception of different wavelengths
    18.
    发明授权
    BSI image sensor package with variable-height silicon for even reception of different wavelengths 有权
    BSI图像传感器封装，具有可变高度的硅，用于均匀接收不同的波长

    公开(公告)号：US08937361B2

    公开(公告)日：2015-01-20

    申请号：US13114243

    申请日：2011-05-24

    申请人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

    发明人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

    IPC分类号： H01L31/0232 ,  H01L27/146

    CPC分类号： H01L27/14625 ,  H01L27/1461 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

    摘要： A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide.

    摘要翻译： 提供了一种用于背面照明的微电子图像传感器组件及其制造方法。 该组件包括具有在正面暴露的触点的微电子元件和被布置成通过后表面接收不同波长的光的光感测元件。 半导体区域在第一光感测元件和后表面之间具有第一厚度，并且在第二光感测元件和后表面之间具有第二厚度，使得第一和第二光感测元件接收基本上相同强度的光。 提供至少基本上填充与至少一个光感测元件相邻的半导体区域的空间的电介质区域。 电介质区域可以包括至少一个光导。