公开(公告)号：US20130063918A1

公开(公告)日：2013-03-14

申请号：US13232436

申请日：2011-09-14

申请人： Belgacem Haba ,  Kishor Desai

发明人： Belgacem Haba ,  Kishor Desai

IPC分类号： H05K7/00 ,  B32B38/08 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/17104 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19107 ,  Y10T29/49128 ,  Y10T428/24521 ,  Y10T428/24802 ,  H01L2924/00 ,  H01L2924/00012

摘要： An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

摘要翻译： 互连部件包括第一支撑部分，其具有大致垂直于其表面延伸的多个第一导电通孔，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。 第二支撑部分具有大致垂直于其表面延伸穿过的多个第二导电通路，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。 再分配层设置在第一和第二支撑部分的第二表面之间，将至少一些第一通孔与至少一些第二通孔电连接。 第一和第二支撑部分的热膨胀系数（CTE）可以低于每百万摄氏度（ppm /℃）的百万分之十二。

公开(公告)号：US20060128072A1

公开(公告)日：2006-06-15

申请号：US11011459

申请日：2004-12-13

申请人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

发明人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.

摘要翻译： 形成在集成电路管芯中的保险丝包括：用于连接集成电路管芯上的电路的两个点的导电材料的长度，并且用于通过足以溶解导电的一部分的电流的脉冲来选择性地断开连接 材料; 形成在导电材料的长度上的钝化层; 以及除了钝化层之外还在导电材料长度的一部分上形成的保护涂层，以避免在碰撞过程中从蚀刻剂损坏保险丝。

公开(公告)号：US07041516B2

公开(公告)日：2006-05-09

申请号：US10268361

申请日：2002-10-10

申请人： Sarathy Rajagopalan ,  Kishor Desai ,  John P. McCormick ,  Maniam Alagaratnam

发明人： Sarathy Rajagopalan ,  Kishor Desai ,  John P. McCormick ,  Maniam Alagaratnam

IPC分类号： H01L21/50 ,  G01R31/26

CPC分类号： H01L25/50 ,  H01L22/20 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2224/0401

摘要： A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

摘要翻译： 一种将至少第一集成电路和第二集成电路组装到多芯片模块中的方法。 第一集成电路被附接并电连接到第一基板以形成第一组件，其被测试以确保其正常工作。 第二集成电路被连接并电连接到第二基板以形成第二组件，其也被测试以确保其正常工作。 第一组件被附接并电连接到第二组件以形成多芯片模块。

公开(公告)号：US6133064A

公开(公告)日：2000-10-17

申请号：US322064

申请日：1999-05-27

申请人： Kumar Nagarajan ,  Kishor Desai

发明人： Kumar Nagarajan ,  Kishor Desai

IPC分类号： H01L21/56 ,  H01L23/42 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/42 ,  H01L21/563 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16195

摘要： Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upper portion of the dielectric forms a frame for receiving a heat spreader.

摘要翻译： 公开了与倒装芯片球栅阵列封装相关的方法和装置。 衬底包括其上具有电介质的基底层，使得电介质中的空腔暴露于基底层。 然后将模具安装到基层的暴露部分。 优选地，电介质的上部形成用于接收散热器的框架。

公开(公告)号：US08803269B2

公开(公告)日：2014-08-12

申请号：US13463408

申请日：2012-05-03

申请人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

发明人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

IPC分类号： H01L31/0232 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12

CPC分类号： H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

摘要翻译： 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

公开(公告)号：US20130183008A1

公开(公告)日：2013-07-18

申请号：US13737080

申请日：2013-01-09

申请人： Kalpendu Shastri ,  Soham Pathak ,  Utpal Chakrabarti ,  Vipulkumar Patel ,  Bipin Dama ,  Ravinder Kachru ,  Kishor Desai

发明人： Kalpendu Shastri ,  Soham Pathak ,  Utpal Chakrabarti ,  Vipulkumar Patel ,  Bipin Dama ,  Ravinder Kachru ,  Kishor Desai

IPC分类号： G02B6/42

CPC分类号： G02B6/4292 ,  B82Y20/00 ,  C03C15/00 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/4259 ,  Y10T29/4978

摘要： An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.

摘要翻译： 一种用于在光电子基板和光纤阵列之间提供自对准光耦合的装置，其中基板由透明盖包围，使得相关联的光信号通过透明盖进入和离开布置。 该装置采取两部分连接的光纤阵列组件的形式，其中两个部件独特地配合以形成自对准配置。 在光信号通过的区域中，透明盖附着有板的形式的第一部分。 第一板包括具有围绕其周边的向内逐渐变细的侧壁的中心开口。 第二板也形成为包括中心开口并且具有下突起，其具有向内渐缩的侧壁，与第一板的向内渐缩的侧壁配合形成自对准的连接纤维阵列组件。 然后将纤维阵列以自对准的方式附接到第二板。

公开(公告)号：US20130101250A1

公开(公告)日：2013-04-25

申请号：US13656528

申请日：2012-10-19

申请人： Kishor Desai ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

发明人： Kishor Desai ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

IPC分类号： G02B6/12 ,  H01L33/52

CPC分类号： G02B6/4255 ,  G02B6/12 ,  G02B6/13 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H01L21/50 ,  H01L23/04 ,  H01L23/48 ,  H01L25/167 ,  H01L31/0203 ,  H01L33/52 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/165 ,  H01L2924/16788 ,  H05K1/0268 ,  H05K1/0274 ,  H05K2201/10121 ,  H01L2924/0105 ,  H01L2924/01079

摘要： An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

摘要翻译： 提供了一种光电子组件，其包括用于支撑多个互连的光学和电气部件的基板（通常为硅或玻璃）。 设置一层密封材料以概述衬底的限定的周边区域。 将模制的玻璃盖设置在基底上并结合到基底上，其中模制的玻璃盖构造成产生与限定的基底周边区域匹配的覆盖区。 模制玻璃盖的底表面包括一层接合材料，其在接触时接触基底的密封材料层，形成结合组件。 在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。

公开(公告)号：US20120126389A1

公开(公告)日：2012-05-24

申请号：US12953994

申请日：2010-11-24

申请人： Kishor Desai ,  Belgacem Haba ,  Wael Zohni

发明人： Kishor Desai ,  Belgacem Haba ,  Wael Zohni

IPC分类号： H01L25/07 ,  H01L21/98

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103

摘要： The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.

摘要翻译： 微电子组件包括具有前表面的第一微电子元件，在前表面处暴露的多个触点以及远离前表面的后表面; 第二微电子元件具有面向第一微电子元件的后表面并且突出超过第一微电子元件的边缘的前表面，第二微电子元件具有在其前表面处暴露的多个触点; 位于所述微电子元件的前表面上方的电介质区域，所述电介质区域具有背离所述微电子元件的主表面; 在从第一和第二微电子元件的多个触点延伸的电介质区域内的开口内的金属化通孔; 并且引线沿着介电区域的主表面从通孔暴露在主表面处的端子延伸。

公开(公告)号：US08378478B2

公开(公告)日：2013-02-19

申请号：US12953994

申请日：2010-11-24

申请人： Kishor Desai ,  Belgacem Haba ,  Wael Zohni

发明人： Kishor Desai ,  Belgacem Haba ,  Wael Zohni

IPC分类号： H01L23/02

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103

摘要： The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.

摘要翻译： 微电子组件包括具有前表面的第一微电子元件，在前表面处暴露的多个触点以及远离前表面的后表面; 第二微电子元件具有面向第一微电子元件的后表面并且突出超过第一微电子元件的边缘的前表面，第二微电子元件具有在其前表面处暴露的多个触点; 位于所述微电子元件的前表面上方的电介质区域，所述电介质区域具有背离所述微电子元件的主表面; 在从第一和第二微电子元件的多个触点延伸的电介质区域内的开口内的金属化通孔; 并且引线沿着介电区域的主表面从通孔暴露在主表面处的端子延伸。

公开(公告)号：US20120280344A1

公开(公告)日：2012-11-08

申请号：US13463408

申请日：2012-05-03

申请人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

发明人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

IPC分类号： H01L31/12

CPC分类号： H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

摘要翻译： 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作平台（插入器），用于多个收发器模块的所有部件安装或集成在该平台上，硅插入器的顶表面用作用于定义光信号的参考平面 分离的光学元件之间的路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。