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    High voltage monolithic LED chip
    12.
    发明授权
    High voltage monolithic LED chip 有权

    公开(公告)号：US10115860B2

    公开(公告)日：2018-10-30

    申请号：US15647823

    申请日：2017-07-12

    Applicant: Cree, Inc.

    Inventor： Kevin W. Haberern ,  Matthew Donofrio ,  Bennett Langsdorf ,  Thomas Place ,  Michael John Bergmann

    IPC: H01L31/0256 ,  H01L33/08 ,  H01L33/40 ,  H01L25/075 ,  H01L33/46

    Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.

    LED LAMP AND HYBRID REFLECTOR
    16.
    发明申请
    LED LAMP AND HYBRID REFLECTOR 有权
    LED灯和混合反射器

    公开(公告)号：US20140268808A1

    公开(公告)日：2014-09-18

    申请号：US13828516

    申请日：2013-03-14

    Applicant: CREE, INC.

    Inventor： Gerald H. Negley ,  Matthew Donofrio

    IPC: F21V7/22 ,  F21V3/04

    CPC classification number: F21V7/22 ,  C23C28/00 ,  F21K9/23 ,  F21K9/238 ,  F21V3/04 ,  F21V3/10 ,  F21V19/003 ,  F21V23/006 ,  F21V29/777 ,  F21Y2107/30 ,  F21Y2115/10 ,  G02B5/0816 ,  G02B5/0858

    Abstract: A lamp comprises an enclosure having a reflective surface and an exit surface through which light is emitted from the enclosure and a base. A plurality of LEDs are located in the enclosure and are operable to emit light when energized through an electrical path from the base. The reflective surface comprises a first reflective layer applied to the enclosure and a second reflective layer over the first reflective layer. The first reflective layer is a metalized surface. The second layer comprises a transparent carrier such as silicone mixed with a reflective media such as TiO2, Barium Sulfate and/or ZnO or silver.

    Abstract translation: 灯包括具有反射表面和出射表面的外壳，通过该出射表面，光从外壳和底座发射出去。 多个LED位于外壳中，并且当通过从基座的电路通电时可操作以发光。 反射表面包括施加到外壳的第一反射层和位于第一反射层上的第二反射层。 第一反射层是金属化表面。 第二层包括与反射介质如TiO 2，硫酸钡和/或ZnO或银混合的透明载体，例如硅氧烷。

    LIGHT EMITTING DEVICES HAVING CURRENT REDUCING STRUCTURES
    18.
    发明申请
    LIGHT EMITTING DEVICES HAVING CURRENT REDUCING STRUCTURES 有权
    具有减少电流结构的发光装置

    公开(公告)号：US20130292639A1

    公开(公告)日：2013-11-07

    申请号：US13856928

    申请日：2013-04-04

    Applicant: Cree, Inc.

    Inventor： David Todd Emerson ,  Kevin Haberern ,  Michael John Bergmann ,  David B. Slater, JR. ,  Matthew Donofrio ,  John Edmond

    IPC: H01L33/14

    CPC classification number: H01L33/145 ,  H01L24/05 ,  H01L33/14 ,  H01L33/38 ,  H01L2224/49107 ,  H01L2933/0016

    Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer and an active region between the p-type semiconductor layer and the n-type semiconductor layer. A bond pad is provided on one of the p-type semiconductor layer or the n-type semiconductor layer, opposite the active region, the bond pad being electrically connected to the one of the p-type semiconductor layer or the n-type semiconductor layer. A conductive finger extends from and is electrically connected to the bond pad. A reduced conductivity region is provided in the light emitting device that is aligned with the conductive finger. A reflector may also be provided between the bond pad and the reduced conductivity region. A reduced conductivity region may also be provided in the light emitting device that is not aligned with the bond pad.

    Abstract translation: 发光器件包括p型半导体层，n型半导体层和p型半导体层和n型半导体层之间的有源区。 在与有源区相对的p型半导体层或n型半导体层之一上设置接合焊盘，所述接合焊盘与p型半导体层或n型半导体层中的一者电连接 。 导电指状物从接合焊盘延伸并与其电连接。 在与导电指状物对准的发光器件中设置降低的导电性区域。 还可以在接合焊盘和减小的导电区域之间设置反射器。 还可以在不与接合焊盘对准的发光器件中提供降低的导电性区域。

    SILICON CARBIDE WAFERS WITH RELAXED POSITIVE BOW AND RELATED METHODS
    19.
    发明申请
    SILICON CARBIDE WAFERS WITH RELAXED POSITIVE BOW AND RELATED METHODS 有权

    公开(公告)号：US20210170632A1

    公开(公告)日：2021-06-10

    申请号：US17178532

    申请日：2021-02-18

    Applicant: Cree, Inc.

    Inventor： Simon Bubel ,  Matthew Donofrio ,  John Edmond ,  Ian Currier

    IPC: B28D5/00 ,  H01L29/16

    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.

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