公开(公告)号：US10991861B2

公开(公告)日：2021-04-27

申请号：US15280438

申请日：2016-09-29

Applicant: Cree, Inc.

Inventor： Michael John Bergmann ,  Matthew Donofrio ,  Peter Scott Andrews ,  Colin Blakely ,  Troy Gould ,  Jack Vu

IPC: H01L25/16 ,  H01L33/06 ,  H01L33/10 ,  H01L33/20 ,  H01L33/22 ,  H01L33/38 ,  H01L33/40 ,  H01L33/44 ,  H01L33/48 ,  H01L33/50 ,  H01L33/54 ,  H01L33/60 ,  H01L33/62 ,  H01L25/075 ,  H01L33/32

Abstract: Flip chip LEDs incorporate multi-layer reflectors and light transmissive substrates patterned along an internal surface adjacent to semiconductor layers. A multi-layer reflector may include a metal layer and a dielectric layer containing conductive vias. Portions of a multi-layer reflector may wrap around a LED mesa including an active region, while being covered with passivation material. A substrate patterned along an internal surface together with a multi-layer reflector enables reduction of optical losses. A light transmissive fillet material proximate to edge emitting surfaces of an emitter chip may enable adequate coverage with lumiphoric material. An emitter chip may be elevated with increased thickness of solder material and/or contacts, and may reduce luminous flux loss when reflective materials are present on a submount. Methods for coating emitter chips with lumiphoric material include one or more of angled spray coating, fillet formation prior to spray coating, stencil island coating, and releasable tape coating.

公开(公告)号：US10797201B2

公开(公告)日：2020-10-06

申请号：US16173617

申请日：2018-10-29

Applicant: Cree, Inc.

Inventor： Kevin W. Haberern ,  Matthew Donofrio ,  Bennett Langsdorf ,  Thomas Place ,  Michael John Bergmann

IPC: H01L31/0256 ,  H01L33/08 ,  H01L33/40 ,  H01L25/075 ,  H01L33/46

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.

公开(公告)号：US20190074407A1

公开(公告)日：2019-03-07

申请号：US16173617

申请日：2018-10-29

Applicant: Cree, Inc.

Inventor： Kevin W. Haberern ,  Matthew Donofrio ,  Bennett Langsdorf ,  Thomas Place ,  Michael John Bergmann

IPC: H01L33/08 ,  H01L33/40 ,  H01L25/075

CPC classification number: H01L33/08 ,  H01L25/0753 ,  H01L33/405 ,  H01L33/46 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.

公开(公告)号：US09281445B2

公开(公告)日：2016-03-08

申请号：US14519746

申请日：2014-10-21

Applicant: Cree, Inc.

Inventor： Matthew Donofrio

IPC: H01L33/22 ,  H01L33/32 ,  H01L33/20 ,  H01L33/42 ,  H01L33/38 ,  H01L33/00

CPC classification number: H01L33/22 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/20 ,  H01L33/32 ,  H01L33/382 ,  H01L33/42

Abstract: An LED includes a mesa having a Group III Nitride mesa face and a mesa sidewall, on an underlying LED structure. The mesa face includes Group III Nitride surface features having tops that are defined by mask features, having bottoms, and having sides that extend along crystal planes of the Group III Nitride. The mask features may include a two-dimensional array of dots that are spaced apart from one another. Related fabrication methods are also disclosed.

Abstract translation: LED包括在下面的LED结构上具有III族氮化物台面和台面侧壁的台面。 台面包括III型氮化物表面特征，其具有由掩模特征限定的顶部，具有底部，并且具有沿III族氮化物的晶面延伸的侧面。 掩模特征可以包括彼此间隔开的二维点阵列。 还公开了相关的制造方法。

公开(公告)号：US09115870B2

公开(公告)日：2015-08-25

申请号：US13828516

申请日：2013-03-14

Applicant: Cree, Inc.

Inventor： Gerald H. Negley ,  Matthew Donofrio

IPC: F21V7/00 ,  F21V7/22 ,  F21V3/04 ,  F21K99/00 ,  C23C28/00 ,  F21V19/00 ,  F21V23/00 ,  G02B5/08 ,  F21Y101/02 ,  F21Y111/00 ,  F21V29/77

CPC classification number: F21V7/22 ,  C23C28/00 ,  F21K9/23 ,  F21K9/238 ,  F21V3/04 ,  F21V3/10 ,  F21V19/003 ,  F21V23/006 ,  F21V29/777 ,  F21Y2107/30 ,  F21Y2115/10 ,  G02B5/0816 ,  G02B5/0858

Abstract: A lamp comprises an enclosure having a reflective surface and an exit surface through which light is emitted from the enclosure and a base. A plurality of LEDs are located in the enclosure and are operable to emit light when energized through an electrical path from the base. The reflective surface comprises a first reflective layer applied to the enclosure and a second reflective layer over the first reflective layer. The first reflective layer is a metalized surface. The second layer comprises a transparent carrier such as silicone mixed with a reflective media such as TiO2, Barium Sulfate and/or ZnO or silver.

Abstract translation: 灯包括具有反射表面和出射表面的外壳，通过该出射表面，光从外壳和底座发射出去。 多个LED位于外壳中，并且当通过从基座的电路通电时可操作以发光。 反射表面包括施加到外壳的第一反射层和位于第一反射层上的第二反射层。 第一反射层是金属化表面。 第二层包括与反射介质如TiO 2，硫酸钡和/或ZnO或银混合的透明载体，例如硅氧烷。

公开(公告)号：US20150069430A1

公开(公告)日：2015-03-12

申请号：US14120297

申请日：2014-05-14

Applicant: Cree, Inc.

Inventor： Brian T. Collins ,  Matthew Donofrio ,  Kevin W. Haberern ,  Bennett Langsdorf ,  Anoop Mathew ,  Harry A. Seibel ,  Iliya Todorov ,  Bradley E. Williams

IPC: H01L33/50 ,  H01L27/15

CPC classification number: H01L33/50 ,  H01L33/44

Abstract: A phosphor-converted light emitting device includes a light emitting diode (LED) on a substrate, where the LED comprises a stack of epitaxial layers comprising a p-n junction. A wavelength conversion material is in optical communication with the LED. According to one embodiment of the phosphor-converted light emitting device, a selective filter is adjacent to the wavelength conversion material, and the selective filter comprises a plurality of nanoparticles for absorbing light from the LED not down-converted by the wavelength conversion material. According to another embodiment of the phosphor-converted light emitting device, a perpendicular distance between a perimeter of the LED on the substrate and an edge of the substrate is at least about 24 microns. According to another embodiment of the phosphor-converted light emitting device, the LED comprises a mirror layer on one or more sidewalls thereof for reducing light leakage through the sidewalls.

Abstract translation: 磷光体转换发光器件包括在衬底上的发光二极管（LED），其中LED包括一叠包括p-n结的外延层。 波长转换材料与LED光学通信。 根据荧光体转换发光器件的一个实施例，选择滤光器与波长转换材料相邻，并且选择滤光器包括多个纳米颗粒，用于吸收未被波长转换材料下转换的LED的光。 根据磷光体转换发光器件的另一实施例，衬底上LED的周边与衬底的边缘之间的垂直距离为至少约24微米。 根据荧光体转换发光器件的另一实施例，LED包括在其一个或多个侧壁上的镜层，用于减少通过侧壁的光泄漏。

公开(公告)号：US20140175473A1

公开(公告)日：2014-06-26

申请号：US13758565

申请日：2013-02-04

Applicant: CREE, INC.

Inventor： Matthew Donofrio ,  Barry Rayfield ,  Shaow B. Lin

IPC: H01L33/56 ,  H01L33/50

CPC classification number: H01L33/44 ,  H01L33/507 ,  H01L33/54

Abstract: A light emitting device includes a Light Emitting Diode (LED) having a light emitting surface, a silicon nitride layer on the light emitting surface and a sealed environment surrounding the light emitting surface. The silicon nitride layer may be directly on and cover the light emitting surface. The silicon nitride layer may completely cover the light emitting surface. The silicon nitride layer may provide a substance blocking layer such as a moisture blocking layer and/or a carbon blocking layer that can prevent moisture and/or carbon, such as Volatile Organic Compounds (VOCs) that contain carbon, from reaching the light emitting surface.

Abstract translation: 发光器件包括具有发光表面的发光二极管（LED），发光表面上的氮化硅层和围绕发光表面的密封环境。 氮化硅层可以直接在发光表面上并覆盖发光表面。 氮化硅层可以完全覆盖发光表面。 氮化硅层可以提供可以防止水分和/或碳的物质阻挡层，例如防潮层和/或碳阻挡层，例如含有碳的挥发性有机化合物（VOC）到达发光表面 。

公开(公告)号：US20140167065A1

公开(公告)日：2014-06-19

申请号：US14185589

申请日：2014-02-20

Applicant: CREE, INC.

Inventor： Michael Bergmann ,  Matthew Donofrio ,  Sten Heikman ,  Kevin S. Schneider ,  Kevin W. Haberern ,  John A. Edmond

IPC: H01L33/60 ,  H01L33/32 ,  H01L33/08

CPC classification number: H01L33/60 ,  H01L33/08 ,  H01L33/32 ,  H01L33/382 ,  H01L33/385 ,  H01L33/405 ,  H01L33/46 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2933/0016 ,  H01L2924/00014

Abstract: Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror, such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region. In a further embodiment, the barrier layer is smaller than the mirror such that the periphery of the mirror is at least 40% free of the barrier layer, and the second contact is below the first contact and accessible from the bottom of the chip.

Abstract translation: 本发明的实施例通常涉及通过减少与镜接触相邻的阻挡层的光吸收效果来改进总发射的LED芯片。 在一个实施例中，LED芯片包括一个或多个LED，其中每个LED具有有源区，在有源区下方的第一接触具有高反射镜，以及邻近反射镜的阻挡层。 阻挡层比镜子小，使得其不延伸超出反射镜的周边。 在另一个可能的实施例中，进一步提供绝缘体，其中绝缘体邻近阻挡层并且反射镜的相邻部分未被有源区域或阻挡层接触。 在另一个实施例中，在有源区上提供第二接触。 在另一个实施例中，阻挡层小于反射镜，使得反射镜的周边至少不含阻挡层40％，并且第二触点位于第一触点下方并且可从芯片的底部接近。

公开(公告)号：US08704240B2

公开(公告)日：2014-04-22

申请号：US13856928

申请日：2013-04-04

Applicant: Cree, Inc.

Inventor： David Todd Emerson ,  Kevin Haberern ,  Michael John Bergmann ,  David B. Slater, Jr. ,  Matthew Donofrio ,  John Edmond

IPC: H01L33/00

CPC classification number: H01L33/145 ,  H01L24/05 ,  H01L33/14 ,  H01L33/38 ,  H01L2224/49107 ,  H01L2933/0016

Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer and an active region between the p-type semiconductor layer and the n-type semiconductor layer. A bond pad is provided on one of the p-type semiconductor layer or the n-type semiconductor layer, opposite the active region, the bond pad being electrically connected to the one of the p-type semiconductor layer or the n-type semiconductor layer. A conductive finger extends from and is electrically connected to the bond pad. A reduced conductivity region is provided in the light emitting device that is aligned with the conductive finger. A reflector may also be provided between the bond pad and the reduced conductivity region. A reduced conductivity region may also be provided in the light emitting device that is not aligned with the bond pad.

Abstract translation: 发光器件包括p型半导体层，n型半导体层和p型半导体层和n型半导体层之间的有源区。 在与有源区相对的p型半导体层或n型半导体层之一上设置接合焊盘，所述接合焊盘与p型半导体层或n型半导体层中的一者电连接 。 导电指状物从接合焊盘延伸并与其电连接。 在与导电指状物对准的发光器件中设置降低的导电性区域。 还可以在接合焊盘和减小的导电区域之间设置反射器。 还可以在不与接合焊盘对准的发光器件中提供降低的导电性区域。

公开(公告)号：US10562130B1

公开(公告)日：2020-02-18

申请号：US16410487

申请日：2019-05-13

Applicant: Cree, Inc.

Inventor： Matthew Donofrio ,  John Edmond ,  Harshad Golakia ,  Eric Mayer

IPC: H01L21/67 ,  H01L21/268 ,  H01L29/16 ,  B23K26/53 ,  B23K26/03 ,  B28D5/00 ,  B23K26/40 ,  H01L21/02

Abstract: A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One potential action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another potential action includes forming additional subsurface laser damage at the first depth position. The substrate surface is illuminated with a diffuse light source arranged perpendicular to a primary substrate flat and positioned to a first side of the substrate, and imaged with an imaging device positioned to an opposing second side of the substrate.