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    Method to make a weight compensating/tuning layer on a substrate
    11.
    发明申请
    Method to make a weight compensating/tuning layer on a substrate 失效
    在基板上制作重量补偿/调谐层的方法

    公开(公告)号：US20050070119A1

    公开(公告)日：2005-03-31

    申请号：US10675587

    申请日：2003-09-29

    申请人： Theodore Doros ,  Krishna Seshan

    发明人： Theodore Doros ,  Krishna Seshan

    IPC分类号： B81B3/00 ,  H01L21/30 ,  H01L21/31 ,  H03H3/04 ,  H04B7/26 ,  H04Q7/22

    CPC分类号： B81B3/0072 ,  B81C2201/0109

    摘要： Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.

    摘要翻译： 本发明的实施例在其表面拓扑变化的结构（例如，具有一层或多层材料的硅晶片（例如膜））上形成体重补偿/调谐层。 表面拓扑的变化采取厚薄的材料区域的形式。 重量补偿/调谐层分别包括对应于厚和薄区域的窄且宽的区域。

    Diode and transistor design for high speed I/O
    14.
    发明授权
    Diode and transistor design for high speed I/O 失效
    用于高速I / O的二极管和晶体管设计

    公开(公告)号：US6137143A

    公开(公告)日：2000-10-24

    申请号：US107351

    申请日：1998-06-30

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002

    摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

    摘要翻译： 一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。 此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护 电路到性能电路。

    Instrument for the measurement of electrical characteristics during manufacturing processes
    15.
    发明授权
    Instrument for the measurement of electrical characteristics during manufacturing processes 失效
    用于测量制造过程中电气特性的仪器

    公开(公告)号：US5504434A

    公开(公告)日：1996-04-02

    申请号：US453590

    申请日：1995-05-30

    申请人： Dominic J. Schepis ,  Krishna Seshan

    发明人： Dominic J. Schepis ,  Krishna Seshan

    IPC分类号： H01L21/48 ,  H01L21/66 ,  G01R31/26

    CPC分类号： H01L22/14 ,  H01L21/485 ,  H01L22/22

    摘要： A measurement technique and instrument using rectangular pulse trains of differing repetition rates and synchronously operated lock-in amplifiers to reject electrical noise and capture changes in resistance and capacitance of an electrical element even during a short electrical pulse applied thereto or in the presence of high levels of electrical noise. Particular applications are for electrical programming of fuses and repair of conductors by material deposition.

    摘要翻译： 使用不同重复率的矩形脉冲串和同步操作的锁定放大器的测量技术和仪器，以抵抗电气噪声，并捕获电子元件的电阻和电容的变化，即使在施加到其上的短电脉冲中或存在高电平 的电噪声。 特殊应用是用于熔丝的电气编程和通过材料沉积修复导体。

    Method of fabricating a linearized output driver and terminator
    16.
    发明授权
    Method of fabricating a linearized output driver and terminator 有权
    制造线性化输出驱动器和终端器的方法

    公开(公告)号：US07250333B2

    公开(公告)日：2007-07-31

    申请号：US10394977

    申请日：2003-03-20

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

    Diode and transistor design for high speed I/O
    17.
    发明授权
    Diode and transistor design for high speed I/O 失效

    公开(公告)号：US07012304B1

    公开(公告)日：2006-03-14

    申请号：US09651385

    申请日：2000-08-29

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.