公开(公告)号：US10340183B1

公开(公告)日：2019-07-02

申请号：US15860318

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Shafaat Ahmed ,  Zhiguo Sun ,  Jiehui Shu ,  Dinesh R. Koli ,  Wei-Tsu Tseng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US20180323067A1

公开(公告)日：2018-11-08

申请号：US15587597

申请日：2017-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xusheng Yu ,  John H. Zhang ,  Xiaoqiang Zhang

IPC: H01L21/033 ,  H01L23/525 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31116 ,  H01L21/768 ,  H01L23/5256 ,  H01L23/53214 ,  H01L23/53228

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.

公开(公告)号：US09905472B1

公开(公告)日：2018-02-27

申请号：US15440072

申请日：2017-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Haifeng Sheng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/088 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.

公开(公告)号：US09865681B1

公开(公告)日：2018-01-09

申请号：US15453170

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John Zhang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/30604 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568

Abstract: Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.

公开(公告)号：US09704746B1

公开(公告)日：2017-07-11

申请号：US15235892

申请日：2016-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Archana Subramaniyan

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer.

公开(公告)号：US10833171B1

公开(公告)日：2020-11-10

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L29/66 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US20200335600A1

公开(公告)日：2020-10-22

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US10811409B2

公开(公告)日：2020-10-20

申请号：US16161620

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Guowei Xu ,  Jian Gao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

公开(公告)号：US10784195B2

公开(公告)日：2020-09-22

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.