公开(公告)号：US09177803B2

公开(公告)日：2015-11-03

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。

公开(公告)号：US10466126B2

公开(公告)日：2019-11-05

申请号：US15906368

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: G01L9/00 ,  B81B3/00 ,  B81C1/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to pressure sensors and methods of manufacture. The structure includes: a top membrane of semiconductor material having edges defined by epitaxial material and a liner material; a back gate under the top membrane; and a cavity defined between the top membrane and the back gate.

公开(公告)号：US10032891B2

公开(公告)日：2018-07-24

申请号：US15498652

申请日：2017-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L27/115 ,  H01L27/088 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/11536 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11521

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

公开(公告)号：US09837439B1

公开(公告)日：2017-12-05

申请号：US15235256

申请日：2016-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul

IPC: H01L27/12 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L27/1207 ,  H01L23/50 ,  H01L27/0288

Abstract: The present disclosure provides a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region, wherein the SOI region and the hybrid region are separated by at least one isolation structure, the SOI region being formed by a semiconductor layer provided over a substrate material and a buried insulating material interposed between the semiconductor layer and the substrate material, a semiconductor device provided in the SOI region, the semiconductor device comprising a gate structure and source and drain regions formed adjacent to the gate structure, and a diode structure provided in the hybrid region, the diode structure comprising a well region doped with dopants of a first conductivity type and a well portion doped with dopants of a second conductivity type embedded into the well region in the hybrid region.

公开(公告)号：US09748259B1

公开(公告)日：2017-08-29

申请号：US15053485

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/1207 ,  H01L28/00 ,  H01L29/42336 ,  H01L29/42352

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US20170162557A1

公开(公告)日：2017-06-08

申请号：US14958150

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Juergen Faul

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L27/0222 ,  G05F3/205 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/40 ,  H01L29/665 ,  H01L29/945

Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.

公开(公告)号：US09666589B1

公开(公告)日：2017-05-30

申请号：US15075352

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/11541 ,  H01L27/11521 ,  H01L27/11536

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.

公开(公告)号：US09093526B2

公开(公告)日：2015-07-28

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L21/311 ,  H01L29/78 ,  H01L21/314 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US09064733B2

公开(公告)日：2015-06-23

申请号：US14590076

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Frank Jakubowski ,  Juergen Faul

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/1104 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66969

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract translation: 器件包括位于半导体衬底中的第一和第二间隔开的有源区，位于第一和第二间隔开的有源区之间的隔离区和位于第一有源区上的栅极绝缘材料层。 第一导线特征从第一有源区连续延伸并跨越隔离区到第二有源区，其中第一导线特征包括位于第一有源区上的栅极绝缘材料层正上方的第一部分， 以及与第二有源区域导电接触的第二部分。

公开(公告)号：US20140264617A1

公开(公告)日：2014-09-18

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。