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115 条记录 (耗时 0.026 秒)

    On-Chip RF Shields with Through Substrate Conductors
    12.
    发明申请
    On-Chip RF Shields with Through Substrate Conductors 有权
    带有基板导体的片上RF屏蔽

    公开(公告)号：US20100078771A1

    公开(公告)日：2010-04-01

    申请号：US12242521

    申请日：2008-09-30

    申请人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Oliver Nagy

    发明人： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Oliver Nagy

    IPC分类号： H01L23/552 ,  H01L21/44

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.

    摘要翻译： 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，芯片上的系统包括设置在基板的第一部分上的RF部件，设置在基板的第二部分上的半导体部件，共享公共边界的半导体部件和RF部件。 芯片上的系统还包括通过设置在基板中的基板导体，连接到地电位节点的贯穿基板导体，围绕RF元件设置的贯穿基板导体，围绕RF电路形成围栏。

    Three-dimensional multichip module
    17.
    发明授权
    Three-dimensional multichip module 有权
    三维多芯片模块

    公开(公告)号：US07986033B2

    公开(公告)日：2011-07-26

    申请号：US12124335

    申请日：2008-05-21

    申请人： Hans-Joachim Barth

    发明人： Hans-Joachim Barth

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  H01L23/34 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

    摘要： A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.

    摘要翻译： 三维多芯片模块包括具有至少一个第一高温功能区和一个第一低温功能区的第一集成电路芯片和至少一个具有第二高温功能区和第二高温功能区的第二集成电路芯片 低温功能区。 第二高温功能区与第一低温功能区相对。 作为替代，也可以在第一和第二芯片之间设置至少一个仅具有一个低温功能区的低温芯片。

    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    20.
    发明申请
    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100176479A1

    公开(公告)日：2010-07-15

    申请号：US12354480

    申请日：2009-01-15

    申请人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

    发明人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

    IPC分类号： H01L29/68 ,  H01L21/762

    CPC分类号： H01L27/11 ,  G03F7/40 ,  G03F7/7035 ,  H01L21/32139

    摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.

    摘要翻译： 一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在 抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有 初始宽度。 该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分 硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。