公开(公告)号：US20190067564A1

公开(公告)日：2019-02-28

申请号：US16102522

申请日：2018-08-13

Applicant: IMEC vzw

Inventor： Johan Swerts ,  Kiroubanand Sankaran ,  Tsann Lin ,  Geoffrey Pourtois

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer comprising CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer comprising MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

公开(公告)号：US09982360B2

公开(公告)日：2018-05-29

申请号：US14486678

申请日：2014-09-15

Applicant: IMEC VZW

Inventor： Cedric Huyghebaert ,  Philippe M. Vereecken ,  Geoffrey Pourtois

IPC: C25F5/00 ,  C01B32/19 ,  C01B32/194 ,  H01L21/18 ,  B32B37/00 ,  B32B38/00

CPC classification number: C25F5/00 ,  B32B37/025 ,  B32B38/0008 ,  C01B32/19 ,  C01B32/194 ,  H01L21/187 ,  Y10T428/30

Abstract: A method for transferring a graphene layer from a metal substrate to a second substrate is provided comprising: providing a graphene layer on the metal substrate, adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer, treating the metal substrate having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate, transferring the graphene layer to the second substrate, and optionally reusing the metal substrate by repeating the aforementioned steps.

公开(公告)号：US20170179263A1

公开(公告)日：2017-06-22

申请号：US15380887

申请日：2016-12-15

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Geoffrey Pourtois ,  Anh Khoa Lu ,  Cedric Huyghebaert

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/16 ,  H01L29/24 ,  H01L29/402 ,  H01L29/778 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

公开(公告)号：US20150340503A1

公开(公告)日：2015-11-26

申请号：US14719995

申请日：2015-05-22

Applicant: IMEC VZW ,  Sony Corporation

Inventor： Hideki Minari ,  Shinichi Yoshida ,  Geoffrey Pourtois ,  Matty Caymax ,  Eddy Simoen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/7851

Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.

Abstract translation: 公开了在分离浅沟槽隔离（STI）结构和暴露半导体衬底的间隙内产生III-V鳍结构的方法，该方法包括提供半导体衬底，在半导体衬底中提供至少两个相同的STI结构， 暴露半导体衬底的间隙，其中所述间隙由所述至少两个相同的STI结构限定，并且在所述暴露的半导体衬底上的所述间隙内产生III-V鳍结构，并且提供至少与每个 所述至少两个相同的STI结构的侧壁和所述III-V鳍结构的侧壁，并且其中所述半导体衬底是Si衬底。

公开(公告)号：US20230382756A1

公开(公告)日：2023-11-30

申请号：US18324791

申请日：2023-05-26

Applicant: IMEC VZW

Inventor： Michiel Jan Van Setten ,  Geoffrey Pourtois ,  Hendrik F.W. Dekkers ,  Gouri Sankar Kar

IPC: C01G9/03 ,  H01L29/786

CPC classification number: C01G9/03 ,  H01L29/78693 ,  C01P2002/02

Abstract: A mixed metal oxide and methods for making the mixed metal oxide are disclosed. The mixed metal oxide includes metal and metalloid elements including 0.40 to 0.70 parts by mole Mg, 0.30 to 0.60 parts by mole Zn, and 0.00 to 0.30 parts by mole of other elements selected from metals and metalloids, wherein less than 0.01 parts by mole of the other elements is Al, and wherein less than 0.04 parts by mole of the other elements is Ga. The sum of all parts by mole of Mg, Zn, and the other elements may amount to about 1.00. The mixed metal oxide additionally includes) oxygen and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.

公开(公告)号：US10050192B2

公开(公告)日：2018-08-14

申请号：US15373342

申请日：2016-12-08

Applicant: IMEC VZW

Inventor： Johan Swerts ,  Kiroubanand Sankaran ,  Tsann Lin ,  Geoffrey Pourtois

IPC: H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01L43/12

Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer including CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer including MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

公开(公告)号：US20180108734A1

公开(公告)日：2018-04-19

申请号：US15787289

申请日：2017-10-18

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Hao Yu ,  Geoffrey Pourtois

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/267 ,  H01L29/66 ,  H01L29/36 ,  H01L29/205 ,  H01L29/786

CPC classification number: H01L29/0847 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/205 ,  H01L29/267 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/452 ,  H01L29/456 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78681

Abstract: Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material.

公开(公告)号：US09899501B2

公开(公告)日：2018-02-20

申请号：US15380887

申请日：2016-12-15

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Geoffrey Pourtois ,  Anh Khoa Lu ,  Cedric Huyghebaert

IPC: H03K3/01 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/16 ,  H01L29/24 ,  H01L29/402 ,  H01L29/778 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

公开(公告)号：US20170170390A1

公开(公告)日：2017-06-15

申请号：US15373342

申请日：2016-12-08

Applicant: IMEC VZW

Inventor： Johan Swerts ,  Kiroubanand Sankaran ,  Tsann Lin ,  Geoffrey Pourtois

IPC: H01L43/08 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer comprising CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer comprising MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

公开(公告)号：US09608094B2

公开(公告)日：2017-03-28

申请号：US14841566

申请日：2015-08-31

Applicant: IMEC VZW

Inventor： Anne S. Verhulst ,  Geoffrey Pourtois ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/94 ,  H01L29/772 ,  H01L29/775 ,  H01L29/778 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.