公开(公告)号：US20160316567A1

公开(公告)日：2016-10-27

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H05K3/32 ,  H05K1/11 ,  H05K1/02 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

Abstract translation: 半导体模块包括电路板和埋入电路板中的功率半导体芯片。 功率半导体芯片具有第一负载电极。 半导体模块还包括电连接到第一负载电极的电源端子连接器。 嵌入式功率半导体芯片横向定位在电源端子连接器的覆盖区域内。

公开(公告)号：US20230369160A1

公开(公告)日：2023-11-16

申请号：US17742666

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Kushal Kshirsagar ,  Eung San Cho ,  Arun Kumar Gnanappa ,  Wenkang Huang ,  Angela Kessler ,  Marcel Rene Mueller ,  Stephen Pullen

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: A semiconductor assembly includes a device carrier that includes a dielectric core region and a plurality of contact pads disposed on an upper surface, a semiconductor device package having a plurality of lower surface terminals, a discrete passive element comprising a main body and a pair of leads, and a region of gap filler material, wherein the semiconductor device package is mounted on the device carrier with the lower surface terminals facing and electrically connected to a group of the contact pads, wherein the discrete passive element is mounted on the device carrier with the pair of leads electrically connecting with contact surfaces on the device carrier, and wherein the region of gap filler material is arranged between a lower surface of the main body and the upper surface of the semiconductor device package and thermally couples the semiconductor device package to the discrete passive element.

公开(公告)号：US20230197577A1

公开(公告)日：2023-06-22

申请号：US18082238

申请日：2022-12-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Josef Höglauer ,  Angela Kessler ,  Claus Waechter

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49534 ,  H01L25/16 ,  H01L25/50

Abstract: A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.

公开(公告)号：US10211133B2

公开(公告)日：2019-02-19

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US10128180B2

公开(公告)日：2018-11-13

申请号：US15821879

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/12 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495 ,  H01L23/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US10074590B1

公开(公告)日：2018-09-11

申请号：US15649459

申请日：2017-07-13

Applicant: Infineon Technologies AG

Inventor： Mark Pavier ,  Wolfram Hable ,  Angela Kessler ,  Michael Sielaff ,  Anton Pugatschow ,  Charles Rimbert-Riviere ,  Marco Sobkowiak

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  B60R16/02

CPC classification number: H01L23/3735 ,  B60R16/02 ,  H01L21/4807 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/15 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/48139 ,  H01L2224/48175 ,  H01L2224/4846 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/43848

Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.

公开(公告)号：US20180138111A1

公开(公告)日：2018-05-17

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/83906 ,  H01L2924/014

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US09633927B2

公开(公告)日：2017-04-25

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US09536816B2

公开(公告)日：2017-01-03

申请号：US14815367

申请日：2015-07-31

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Eduard Knauer ,  Rudolf Lehner ,  Wolfgang Schober ,  Sigrid Schultes

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/492 ,  H01L23/498 ,  H01L21/56 ,  H01L23/36 ,  H01L23/373 ,  H01L23/40

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5389 ,  H01L2224/32225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric connection structure mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and partially encapsulating the at least one electric connection structure so that part of a surface of the at least one electric connection structure is exposed to an environment, and a mounting provision configured for mounting the electronic device at a periphery device.

Abstract translation: 一种电子设备，包括具有安装表面的载体，安装在所述安装表面上的至少一个电子芯片，安装在所述安装表面上的至少一个电连接结构，至少部分地封装所述载体和所述至少一个电子芯片的密封剂， 并且部分地封装所述至少一个电连接结构，使得所述至少一个电连接结构的表面的一部分暴露于环境;以及安装配置，用于将所述电子设备安装在周边设备。

公开(公告)号：US11848262B2

公开(公告)日：2023-12-19

申请号：US17176678

申请日：2021-02-16

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

IPC: H01L23/498 ,  H01L25/07 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.