公开(公告)号：US20190355843A1

公开(公告)日：2019-11-21

申请号：US16475220

申请日：2017-02-02

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H04B1/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

Abstract: An apparatus, an integrated circuit die, and a method of fabricating a group III-nitride (III-N) integrated RF front-end circuit are disclosed. The apparatus includes a III-N integrated radio frequency (RF) front-end circuit that includes a semiconductor substrate, a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate. The III-N integrated RF front-end circuit is to be coupled to an antenna.

公开(公告)号：US20190189611A1

公开(公告)日：2019-06-20

申请号：US16322082

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861 ,  H01L29/417 ,  H01L29/205 ,  H01L29/167 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/08 ,  C23C16/30 ,  C23C16/04

CPC classification number: H01L27/0255 ,  C23C16/042 ,  C23C16/303 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/8258 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/66136 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.

公开(公告)号：US20180350921A1

公开(公告)日：2018-12-06

申请号：US15771985

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY

IPC: H01L29/267 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02568 ,  H01L21/02609 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/78681

Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.

公开(公告)号：US20180331191A1

公开(公告)日：2018-11-15

申请号：US15777140

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/765

CPC classification number: H01L29/404 ,  H01L21/765 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.

公开(公告)号：US20180323298A1

公开(公告)日：2018-11-08

申请号：US15773422

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/78

Abstract: III-N transistor including a vertically-oriented lightly-doped III-N drift region between an overlying III-N 2DEG channel and an underlying heavily-doped III-N drain. In some embodiments, the III-N transistors are disposed over a silicon substrate. In some embodiments, lateral epitaxial overgrowth is employed to form III-N islands self-aligned with the vertically-oriented drift region. A gate electrode disposed over a portion of a III-N island may modulate a 2DEG within a channel region of the III-N island disposed above the III-N drift region. Charge carriers in the 2DEG channel may be swept into the drift region toward the drain. Topside contacts to each of the gate, source, and drain may be pitch scaled independently of a length of the drift region.

公开(公告)号：US20170236936A1

公开(公告)日：2017-08-17

申请号：US15499794

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L21/762 ,  H01L29/34 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/7624 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US20170012117A1

公开(公告)日：2017-01-12

申请号：US15120496

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，由第一过渡金属二硫属元素（TMD）材料形成的第一阻挡层，由第二TMD材料形成的晶体管沟道和由第三TMD材料形成的第二阻挡层。 第一势垒可以设置在晶体管沟道和柔性衬底之间，晶体管沟道可以设置在第二栅极和第一势垒之间，晶体管沟道的带隙可能小于第一势垒的带隙，而小于 第二个屏障的带隙。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20150325481A1

公开(公告)日：2015-11-12

申请号：US14798380

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/8258 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract translation: 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够给出给定布局区域的显着的驱动电流。

公开(公告)号：US20250089312A1

公开(公告)日：2025-03-13

申请号：US18244090

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Marko RADOSAVLJEVIC ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Jeong Dong KIM ,  Scott MOKLER

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.