公开(公告)号：US20220415780A1

公开(公告)日：2022-12-29

申请号：US17356056

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： William HSU ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Vadym KAPINUS ,  Robert BIGWOOD ,  Nidhi KHANDELWAL ,  Henning HAFFNER ,  Kevin FISCHER

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

公开(公告)号：US20210090997A1

公开(公告)日：2021-03-25

申请号：US16579088

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Mohit K. HARAN ,  Reken PATEL ,  Richard E. SCHENKER ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

公开(公告)号：US20200373201A1

公开(公告)日：2020-11-26

申请号：US16421184

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Mohit K. HARAN ,  Gopinath BHIMARASETTI

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L23/522

Abstract: Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.

公开(公告)号：US20240213250A1

公开(公告)日：2024-06-27

申请号：US18088547

申请日：2022-12-24

Applicant: INTEL CORPORATION

Inventor： Shao Ming KOH ,  Sudipto NASKAR ,  Leonard P. GULER ,  Patrick MORROW ,  Richard E. SCHENKER ,  Walid M. HAFEZ ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Jeanne L. LUCE ,  Dan S. LAVRIC ,  Jack T. KAVALIEROS ,  Matthew PRINCE ,  Lars LIEBMANN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.

公开(公告)号：US20240105599A1

公开(公告)日：2024-03-28

申请号：US17955511

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vishal TIWARI ,  Tahir GHANI ,  Mohit K. HARAN ,  Desalegne B. TEWELDEBRHAN

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/4232

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

公开(公告)号：US20240006322A1

公开(公告)日：2024-01-04

申请号：US18370198

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20230207623A1

公开(公告)日：2023-06-29

申请号：US17561715

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Mohit K. HARAN ,  Mauro J. KOBRINSKY ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6675 ,  H01L29/78672

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.

公开(公告)号：US20230197722A1

公开(公告)日：2023-06-22

申请号：US17558026

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Mohit K. HARAN ,  Leonard P. GULER ,  Pratik PATEL ,  Tahir GHANI ,  Anand S. MURTHY ,  Makram ABD EL QADER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

公开(公告)号：US20220416039A1

公开(公告)日：2022-12-29

申请号：US17357711

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  David J. TOWNER ,  Orb ACTON ,  Jitendra Kumar JHA ,  YenTing CHIU ,  Mohit K. HARAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/49

Abstract: An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

公开(公告)号：US20220406778A1

公开(公告)日：2022-12-22

申请号：US17353263

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Mohammad HASAN ,  Reken PATEL ,  Sean PURSEL ,  Jake JAFFE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.