公开(公告)号：US20190102320A1

公开(公告)日：2019-04-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US10088880B2

公开(公告)日：2018-10-02

申请号：US14837372

申请日：2015-08-27

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Muthukumar P. Swaminathan ,  Doyle Rivers

IPC: G06F1/20 ,  G06F1/32

Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

公开(公告)号：US10452312B2

公开(公告)日：2019-10-22

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Muthukumar P. Swaminathan ,  Alaa R. Alameldeen ,  Kunal A. Khochare ,  Jason A. Gayman

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/26

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US10241912B2

公开(公告)日：2019-03-26

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/0811 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00 ,  G06F12/0895

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20180285020A1

公开(公告)日：2018-10-04

申请号：US15475341

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Muthukumar P. Swaminathan ,  Kunal A. Khochare

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0688 ,  G06F13/1668 ,  G11C8/12 ,  G11C16/08 ,  G11C16/20

Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

公开(公告)号：US20180189207A1

公开(公告)日：2018-07-05

申请号：US15857992

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US09934859B1

公开(公告)日：2018-04-03

申请号：US15391763

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Prashant S. Damle ,  Kunal A. Khochare ,  Philip Hillier ,  Jeffrey W. Ryden ,  Richard P. Mangold

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.

公开(公告)号：US09619408B2

公开(公告)日：2017-04-11

申请号：US15081164

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/00 ,  G06F13/16 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0897 ,  G06F9/46 ,  G06F13/40 ,  G06F13/42 ,  G06F12/00

CPC classification number: G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.