公开(公告)号：US20200245472A1

公开(公告)日：2020-07-30

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Sandeep GAAN ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Ke LIU ,  Suddhasattwa NAD ,  Marcel A. WALL ,  Rahul N. MANEPALLI ,  Ravindra V. TANIKELLA

IPC: H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  C23C18/16 ,  C23C18/18 ,  C23C18/38

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213111A1

公开(公告)日：2024-06-27

申请号：US18088360

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Je-Young CHANG ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Brandon C. MARIN ,  Suddhasattwa NAD

IPC: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/49816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. In an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. In an embodiment, the lid seals the channel between a first end and a second end of the channel.

公开(公告)号：US20240186202A1

公开(公告)日：2024-06-06

申请号：US18415268

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/53295 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230197660A1

公开(公告)日：2023-06-22

申请号：US17558297

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yue DENG ,  Jung Kyu HAN ,  Liang HE ,  Gang DUAN ,  Rahul N. MANEPALLI

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2924/014

Abstract: A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

公开(公告)号：US20230088392A1

公开(公告)日：2023-03-23

申请号：US17481258

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Rahul N. MANEPALLI ,  Ravindra TANIKELLA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.

公开(公告)号：US20230087838A1

公开(公告)日：2023-03-23

申请号：US17479033

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Ravindra TANIKELLA ,  Sameer PAITAL ,  Gang DUAN

IPC: H01L23/29 ,  C03C17/32

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.

公开(公告)号：US20210043580A1

公开(公告)日：2021-02-11

申请号：US17078897

申请日：2020-10-23

Applicant: Intel Corporation

Inventor： Jesse C. JONES ,  Gang DUAN ,  Jason GAMBA ,  Yosuke KANAOKA ,  Rahul N. MANEPALLI ,  Vishal SHAJAN

IPC: H01L23/544 ,  H01L23/538 ,  H01L21/762

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20210035818A1

公开(公告)日：2021-02-04

申请号：US16525985

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Wei-Lun K. JEN ,  Steve S. CHO ,  Jason M. GAMBA ,  Javier SOTO GONZALEZ

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US20190393172A1

公开(公告)日：2019-12-26

申请号：US16481392

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

公开(公告)号：US20180005945A1

公开(公告)日：2018-01-04

申请号：US15197577

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13155 ,  H01L2224/13599 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/15192

Abstract: Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.