公开(公告)号：US20250126814A1

公开(公告)日：2025-04-17

申请号：US18984454

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H10D1/20 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.

公开(公告)号：US20250120102A1

公开(公告)日：2025-04-10

申请号：US18984426

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H10D1/20 ,  H01L23/15 ,  H01L23/538 ,  H01L25/18

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.

公开(公告)号：US20250006623A1

公开(公告)日：2025-01-02

申请号：US18217056

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Shuqi Lai ,  Jieying Kong ,  Dilan Seneviratne ,  Whitney Bryks

IPC: H01L23/498

Abstract: Microelectronic integrated circuit package structures include one or more integrated circuit (IC) package metallization levels comprising metallization features. A dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. A plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix material.

公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC: B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC classification number: B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US20240113072A1

公开(公告)日：2024-04-04

申请号：US17957349

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Whitney Bryks ,  Kristof Darmawikarta ,  Gang Duan ,  Benjamin Duong ,  Srinivas Pietambaram

IPC: H01L23/00 ,  B23K26/364 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L24/97 ,  B23K26/364 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  B23K2103/54 ,  H01L21/561 ,  H01L21/565 ,  H01L2224/08238 ,  H01L2224/16235 ,  H01L2924/3512

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, and a sidewall between the first surface and the second surface. A build-up layer is on at least the first surface. A plurality of regions is on the sidewall. Each region comprises a cavity in the sidewall, wherein the cavity spans a first distance in a first direction from the first surface toward the second surface. In addition, the cavity comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth.

公开(公告)号：US20220139792A1

公开(公告)日：2022-05-05

申请号：US17085177

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Whitney Bryks ,  Sarah Blythe ,  Peumie Abeyratne Kuragama ,  Junxin Wang

IPC: H01L23/29 ,  H01L23/18 ,  H01L23/31 ,  H01L23/522

Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

公开(公告)号：US20250125201A1

公开(公告)日：2025-04-17

申请号：US18984438

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H01L23/15 ,  H01L23/18 ,  H01L23/498 ,  H01L23/64

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. The example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.

公开(公告)号：US20250112175A1

公开(公告)日：2025-04-03

申请号：US18477638

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jesse C. Jones ,  Yosef Kornbluth ,  Mitchell Page ,  Soham Agarwal ,  Fanyi Zhu ,  Shuren Qu ,  Hanyu Song ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Bai Nie ,  Nicholas Haehn ,  Astitva Tripathi ,  Mohamed R. Saber ,  Sheng Li ,  Pratyush Mishra ,  Benjamin T. Duong ,  Kari Hernandez ,  Praveen Sreeramagiri ,  Yi Li ,  Ibrahim El Khatib ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Haobo Chen ,  Robin Shea McRee ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L25/065

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

公开(公告)号：US20250022786A1

公开(公告)日：2025-01-16

申请号：US18899851

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Haobo Chen ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Gamba ,  Bohan Shan ,  Robert May ,  Benjamin Taylor Duong ,  Bai Nie ,  Whitney Bryks

IPC: H01L23/498 ,  H01L23/08

Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.

公开(公告)号：US20240178146A1

公开(公告)日：2024-05-30

申请号：US18060080

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Whitney Bryks ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Ravindranath Vithal Mahajan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/13023 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.