公开(公告)号：US20170092573A1

公开(公告)日：2017-03-30

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Daniel N. SOBIESKI ,  Mihir K. ROY ,  William J. LAMBERT

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/00 ,  H01L21/32

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20250022814A1

公开(公告)日：2025-01-16

申请号：US18898492

申请日：2024-09-26

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Sri Chaitra Jyotsna CHAVALI

IPC: H01L23/64 ,  H01F27/28 ,  H01F27/32 ,  H01F41/04 ,  H01F41/12 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.

公开(公告)号：US20240203978A1

公开(公告)日：2024-06-20

申请号：US18085116

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Harish KRISHNAMURTHY ,  Han Wui THEN ,  William J. LAMBERT ,  Jingshu YU

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based clamp structure is above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.

公开(公告)号：US20220102261A1

公开(公告)日：2022-03-31

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20200303822A1

公开(公告)日：2020-09-24

申请号：US16635148

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Jimin YAO ,  Shawna M. LIFF ,  William J. LAMBERT ,  Zhichao ZHANG ,  Robert L. SANKMAN ,  Sri Chaitra J. CHAVALI

IPC: H01Q9/04 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66 ,  H01L23/498

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US20180323708A1

公开(公告)日：2018-11-08

申请号：US15772487

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Mathew MANUSHAROW

IPC: H02M3/155

CPC classification number: H02M3/155 ,  H01L25/10 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10719

Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.

公开(公告)号：US20170012029A1

公开(公告)日：2017-01-12

申请号：US15117708

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： William J. LAMBERT ,  Robert L. SANKMAN ,  Tyler N. OSBORN ,  Charles A. GEALER

IPC: H01L25/11 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L25/117 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5223 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/014

Abstract: An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling capacitor coupled to the TSV's. A method including providing a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; coupling a decoupling capacitor to the backside of the die. An apparatus including a computing device including a package including a microprocessor including a device side and a backside with through silicon vias (TSV's) extending from the device side to the backside, and a decoupling capacitor coupled to the backside of the die; and a printed circuit board, wherein the package is coupled to the printed circuit board.

Abstract translation: 一种包括模具的设备，所述裸片包括从器件侧延伸到所述管芯的背面的多个穿通硅通孔（TSV）; 以及耦合到TSV的去耦电容器。 一种包括提供包括从所述管芯的器件侧延伸到所述管芯的背面的多个穿通硅通孔（TSV）的管芯的方法; 将去耦电容耦合到芯片的背面。 一种包括计算装置的装置，包括包括微处理器的封装，所述微处理器包括从器件侧延伸到背面的通过硅通孔（TSV）的器件侧和背面;以及耦合到管芯背面的去耦电容器; 以及印刷电路板，其中所述封装件耦合到所述印刷电路板。