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公开(公告)号：US20150179508A1
公开(公告)日：2015-06-25
申请号：US14138628
申请日：2013-12-23
Applicant: INTERMOLECULAR INC.
Inventor： Edwin Adhiprakasha , Sean Barstow , Frank Greer , Wenxian Zhu
IPC: H01L21/768 , H01L23/532
CPC classification number: H01L21/76843 , H01L21/2855 , H01L21/28562 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper.
Abstract translation: 本文所述的实施方案提供了钽基铜屏障和形成这种屏障的方法。 提供介电体。 第一层形成在绝缘体的上方。 第一层包括钽。 在第一层上方形成第二层。 第二层包括锰。 在第二层上方形成第三层。 第三层包括铜。
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公开(公告)号：US08873276B2
公开(公告)日：2014-10-28
申请号：US14058518
申请日：2013-10-21
Applicant: Intermolecular Inc.
Inventor： Pragati Kumar , Sean Barstow , Tony P. Chiang , Sandra G Malhotra
CPC classification number: H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。
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13.发明申请Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films 审中-公开原子层沉积的后置过渡金属氧化物薄膜公开(公告)号：US20140273525A1
公开(公告)日：2014-09-18
申请号：US14019961
申请日：2013-09-06
Applicant: Intermolecular, Inc.
Inventor： Kurt Pang , Sean Barstow , Chi-I Lang , Michael Miller , Sandip Niyogi , Prashant B. Phatak
IPC: H01L21/02
CPC classification number: H01L21/76864 , H01L21/02005 , H01L21/02104 , H01L21/02172 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/283 , H01L21/28575 , H01L21/3065 , H01L22/12 , H01L22/14 , H01L27/1462 , H01L27/14643 , H01L27/14698 , H01L29/1606 , H01L29/41 , H01L29/66477 , H01L29/66742 , H01L29/778 , H01L29/786
Abstract: Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30 Å-thick Al2O3 films.
Abstract translation: 通过原子层沉积（ALD）沉积具有适合于高k栅极电介质的低泄漏电流的金属氧化物膜（例如氧化铝）。 金属沉积阶段后的清洗时间为5-15秒，氧化阶段后的吹扫时间延长超过60秒。 延长后氧化吹扫在30Å厚的Al2O3薄膜中产生了数量级的泄漏电流。
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14.发明申请Methods and Systems for Controlling Gate Dielectric Interfaces of MOSFETs 审中-公开控制MOSFET栅极介质界面的方法和系统公开(公告)号：US20140179095A1
公开(公告)日：2014-06-26
申请号：US13725812
申请日：2012-12-21
Applicant: INTERMOLECULAR, INC.
Inventor： Sandip Niyogi , Sean Barstow , Chi-I Lang
IPC: H01L21/28
CPC classification number: H01L21/28255 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
Abstract: Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided. A metallic layer is deposited on the germanium oxide layer. The metallic layer may be nanocrystalline or amorphous. The deposition of the metallic layer causes the germanium oxide layer to be reduced such that a metal oxide layer is formed adjacent to the germanium channel.
Abstract translation: 本文提供的实施例描述了用于形成场效应晶体管的栅极电介质的方法和系统。 提供了在锗通道的表面上包括锗通道和锗氧化物层的衬底。 金属层沉积在氧化锗层上。 金属层可以是纳米晶体或无定形的。 金属层的沉积使得氧化锗层被还原，使得邻近锗通道形成金属氧化物层。
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15.发明申请Method to control amorphous oxide layer formation at interfaces of thin film stacks for memory and logic components 审中-公开控制存储器和逻辑元件薄膜堆叠界面处无定形氧化物层形成的方法公开(公告)号：US20140110764A1
公开(公告)日：2014-04-24
申请号：US13655838
申请日：2012-10-19
Applicant: INTERMOLECULAR INC.
Inventor： Sandip Niyogi , Sean Barstow , Dipankar Pramanik
CPC classification number: H01L21/28202 , B01J2219/0043 , B01J2219/00443 , B01J2219/00635 , B01J2219/00745 , B82Y30/00 , C23C14/04 , C23C16/04 , C23C16/4412 , C23C16/45565 , H01J37/3244 , H01L21/02126 , H01L21/02274 , H01L21/02301 , H01L21/02304 , H01L21/28194 , H01L22/14 , H01L29/513
Abstract: Methods and apparatuses for combinatorial processing are disclosed. Methods of the present disclosure providing a substrate, the substrate comprising a plurality of site-isolated regions. Methods include forming a first capping layer on the surface of a first site-isolated region of the substrate. The methods further include forming a second capping layer on the surface of a second site-isolated region of the substrate. In some embodiments, forming the first and second capping layers include exposing the first and second site-isolated regions to a plasma induced with H2 and hydrocarbon gases. In some embodiments, methods include applying at least one subsequent process to each site-isolated region. In addition, methods include evaluating results of the films post processing.
Abstract translation: 公开了用于组合处理的方法和装置。 提供衬底的本公开的方法，所述衬底包括多个位点隔离区域。 方法包括在衬底的第一位置隔离区域的表面上形成第一覆盖层。 所述方法还包括在所述衬底的第二位置隔离区域的表面上形成第二覆盖层。 在一些实施方案中，形成第一和第二封盖层包括将第一和第二位点隔离区域暴露于由H 2和烃气体引起的等离子体。 在一些实施方案中，方法包括将至少一个后续过程应用于每个位点隔离区域。 此外，方法包括评估胶片后处理的结果。
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Patent Agency Ranking
公开(公告)号：US20140051210A1
公开(公告)日：2014-02-20
申请号：US14062473
申请日：2013-10-24
Applicant: Intermolecular Inc.
Inventor： Sandra G Malhotra , Sean Barstow , Tony P. Chiang , Pragati KUMAR , Prashant B Phatak , Sunil Shanker , Wen Wu
IPC: H01L45/00
CPC classification number: H01L45/1608 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
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公开(公告)号：US09029232B2
公开(公告)日：2015-05-12
申请号：US14281550
申请日：2014-05-19
Applicant: Intermolecular Inc.
Inventor： Sandra G Malhotra , Sean Barstow , Tony P. Chiang , Wayne R French , Pragati Kumar , Prashant B Phatak , Sunil Shanker , Wen Wu
CPC classification number: H01L45/1608 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。
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公开(公告)号：US20150034896A1
公开(公告)日：2015-02-05
申请号：US14488494
申请日：2014-09-17
Applicant: Intermolecular Inc.
Inventor： Pragati Kumar , Sean Barstow , Tony P. Chiang , Sandra G Malhotra
IPC: H01L45/00 , H01L29/861 , H01L27/24
CPC classification number: H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。
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公开(公告)号：US08765567B2
公开(公告)日：2014-07-01
申请号：US14062473
申请日：2013-10-24
Applicant: Intermolecular Inc.
Inventor： Sandra G Malhotra , Sean Barstow , Tony P. Chiang , Pragati Kumar , Prashant B Phatak , Sunil Shanker , Wen Wu
IPC: H01L21/02
CPC classification number: H01L45/1608 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。
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公开(公告)号：US08647894B2
公开(公告)日：2014-02-11
申请号：US13726834
申请日：2012-12-26
Applicant: Intermolecular, Inc.
Inventor： Sandip Niyogi , Sean Barstow
CPC classification number: H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/184 , C23C14/042 , C23C14/0605 , C23C14/185 , C23C14/5806 , H01L21/02422 , H01L21/02672 , H01L21/32051 , H01L21/76823 , H01L23/53276 , H01L2924/0002 , H01L2924/00
Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.
Abstract translation: 提供了一种沉积石墨烯的方法。 该方法包括在衬底的表面上沉积非导电无定形碳层并且以无定型碳上的图案沉积过渡金属。 将衬底在低于500℃的温度下退火，其中退火将设置在过渡金属下面的非导电非晶碳转化成导电无定形碳。 过渡金属的图案的一部分从衬底的表面去除以暴露导电无定形碳。
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