公开(公告)号：US20150214244A1

公开(公告)日：2015-07-30

申请号：US14166155

申请日：2014-01-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Herbert L. Ho ,  Sivananda K. Kanakasabapathy ,  Rishikesh Krishnan ,  Kern Rim

IPC: H01L27/12 ,  H01L27/08 ,  H01L21/324 ,  H01L21/306 ,  H01L21/762 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/1203 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/90

Abstract: Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures.

Abstract translation: 深沟槽电容器和隔离结构的形成通过在蚀刻用于电容器的沟槽和在其中形成电容器之前完成隔离结构来解耦，反之亦然。 这些相应结构的形成的这种解耦允许在深沟槽电容器和隔离结构中使用不同的材料，例如在隔离结构中使用低导磁率或介电常数材料和/或低杨氏模量材料来提供减小的AC电容耦合 跨越隔离结构和/或释放与在深沟槽电容器中使用高介电常数材料或金属 - 绝缘体 - 金属（MIM）结构有关的应力。 这种去耦还允许增加用于深沟槽电容器和隔离结构的反应室的使用效率。

公开(公告)号：US08940558B2

公开(公告)日：2015-01-27

申请号：US13836478

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Wilfried E. A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: H01L21/66 ,  G01B7/06

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

Abstract translation: 提供了在FINFET技术中量化Dgr Dfin的技术。 一方面，一对用于量化一对长沟道FINFET器件之间的Dgr D D的方法包括以下步骤：（a）获得该对中的每个长沟道FINFET器件的Vth值; （b）确定一对长沟道FINFET器件的“Dgr”Vth; 并且（c）使用＆Dgr; Vth来确定一对长沟道FINFET器件之间的Dgr D D D，其中＆Dgr; Vth是Q对之间的差异和一对长沟道FINFET器件之间的栅极电容的函数 ，并且其中Qbody对于该对中的每个长沟道FINFET器件的Dfin和Nch的函数，并且因此＆Dgr; Vth与该对长沟道FINFET器件之间的＆Dgr; Dfin成比例。

公开(公告)号：US20140273298A1

公开(公告)日：2014-09-18

申请号：US13836478

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wilfried E.A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: G01B7/06 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

Abstract translation: 提供了在FINFET技术中量化Dgr Dfin的技术。 一方面，一对用于量化一对长沟道FINFET器件之间的Dgr D D的方法包括以下步骤：（a）获得该对中的每个长沟道FINFET器件的Vth值; （b）确定一对长沟道FINFET器件的“Dgr”Vth; 并且（c）使用＆Dgr; Vth来确定一对长沟道FINFET器件之间的Dgr D D D，其中＆Dgr; Vth是Q对之间的差异和一对长沟道FINFET器件之间的栅极电容的函数 ，并且其中Qbody对于该对中的每个长沟道FINFET器件的Dfin和Nch的函数，并且因此＆Dgr; Vth与该对长沟道FINFET器件之间的＆Dgr; Dfin成比例。

公开(公告)号：US20140124863A1

公开(公告)日：2014-05-08

申请号：US13771255

申请日：2013-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim ,  Ramachandra Divakaruni

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。 还公开了包括体型翅片，SOI型翅片和平面区域的结构。

公开(公告)号：US09917188B2

公开(公告)日：2018-03-13

申请号：US15332408

申请日：2016-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US09735162B2

公开(公告)日：2017-08-15

申请号：US14874390

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/66 ,  H01L21/311 ,  H01L29/417 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

公开(公告)号：US20170053943A1

公开(公告)日：2017-02-23

申请号：US15343387

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/84 ,  H01L21/3065

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

Abstract translation: 一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层 直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构 去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构， 新的门结构围绕四面的部分。

公开(公告)号：US09564445B2

公开(公告)日：2017-02-07

申请号：US14159030

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Bruce B. Doris ,  Herbert L. Ho ,  Ali Khakifirooz ,  Babar A. Khan ,  Shom Ponoth ,  Kern Rim ,  Kehan Tian ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L21/283 ,  H01L21/762

CPC classification number: H01L27/10879 ,  H01L21/283 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/945

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract translation: 可以在半导体鳍片的纵向侧壁之间形成沟槽电容器，并且在半导体鳍片中形成存取晶体管的源极和漏极区域。 在相邻的一对半导体鳍片的端壁之间形成虚拟栅极结构，并且限制通过选择性外延形成的凸起的源极和漏极区域的横向范围。 虚拟栅极结构防止相邻半导体鳍片之间的电短路。 可以在栅极结构和虚拟栅极结构周围形成栅极间隔物。 虚拟栅极结构可以用虚拟替代栅极结构或介电材料部分代替，或者可以保持相同而不取代任何材料。 虚拟栅极结构可以由至少一种电介质材料组成，或者可以包括电浮动的导电材料部分。

公开(公告)号：US09530659B2

公开(公告)日：2016-12-27

申请号：US14603624

申请日：2015-01-23

Applicant: International Business Machines Corporation

Inventor： Kern Rim ,  Junli Wang

IPC: H01L21/308 ,  H01L23/29 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/845 ,  H01L23/291 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure for manufacturing a semiconductor device without damaging the insulator layer during creation of fin field effect transistor (FinFET) devices includes an insulator layer; an active semiconductor layer; and an etch stop layer including material resistant to those processes the etch stop layer is exposed to during creation of a FinFET having fins formed from the active semiconductor layer, such that the etch stop layer and the insulator layer are not damaged during creation of the FinFET; wherein, the etch stop layer is between the insulator layer and the active semiconductor layer.

Abstract translation: 在制造鳍状场效应晶体管（FinFET）器件的同时不会损坏绝缘体层的半导体器件的结构包括绝缘体层; 有源半导体层; 以及蚀刻停止层，其包括在由有源半导体层形成的鳍形成的FinFET的创建期间耐蚀刻停止层暴露于这些处理的材料，使得蚀刻停止层和绝缘体层在形成FinFET期间不被损坏 ; 其中，蚀刻停止层位于绝缘体层和有源半导体层之间。

公开(公告)号：US20160204131A1

公开(公告)日：2016-07-14

申请号：US14595316

申请日：2015-01-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L21/3065 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/84 ,  H01L29/161

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.