公开(公告)号：US09355881B2

公开(公告)日：2016-05-31

申请号：US14182689

申请日：2014-02-18

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Eva-Maria Hess ,  Edward Fuergut ,  Christian Schweiger

IPC: H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L21/762 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/6835 ,  H01L21/268 ,  H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76251 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/467 ,  H01L2224/03 ,  H01L2924/01029

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的载流子和半导体晶片。 该方法包括将介电材料施加到载体或半导体晶片，并通过电介质材料将半导体晶片接合到载体上。 该方法包括处理半导体晶片并从半导体晶片去除载体，使得介电材料保留在半导体晶片上，以提供包括电介质材料的半导体器件。

公开(公告)号：US09275916B2

公开(公告)日：2016-03-01

申请号：US13886283

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/784 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。

公开(公告)号：US09171804B2

公开(公告)日：2015-10-27

申请号：US13681079

申请日：2012-11-19

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L21/58 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US09123806B2

公开(公告)日：2015-09-01

申请号：US14282946

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler

IPC: H01L29/78 ,  H01L23/31 ,  H01L29/06 ,  H01L29/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L29/7827 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/66666 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Abstract translation: 该方法包括提供具有第一主面和与第一主面相对的第二主面的半导体芯片。 半导体芯片包括与第一主面相邻的电气装置。 除了预定义的部分之外，在第二主面处除去半导体芯片的材料，使得非平面表面保留在第二主面。

公开(公告)号：US09082767B2

公开(公告)日：2015-07-14

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/48 ,  H01L23/28 ,  H01L21/58 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract translation: 提供一种嵌入式集成电路封装，所述嵌入式集成电路封装包括：至少一个布置在芯片载体上的芯片，所述至少一个芯片包括多个芯片接触焊盘; 形成在所述芯片载体上并且至少部分地围绕所述至少一个芯片的封装材料; 通过所述封装材料形成的多个电互连，其中每个电互连电连接到芯片接触焊盘; 以及形成在嵌入式集成电路封装的电互连之间的结构，其中该结构增加了电互连之间的耐爬电阻性。

公开(公告)号：US20150061045A1

公开(公告)日：2015-03-05

申请号：US14011621

申请日：2013-08-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Theuss

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2207/07 ,  B81B2207/091 ,  B81C1/00238 ,  B81C1/00301 ,  H01L2224/16225

Abstract: A MEMS device includes a first chip and a MEMS chip. The first chip has a mounting surface and includes at least an integrated circuit. The MEMS chip has a main surface on which a first set of contact pads for contacting the MEMS device and a second set of contact pads for contacting the first chip are arranged. The first chip is mechanically attached and electrically connected to the second set of contact pads via the mounting surface facing the main surface. The mounting surface of the first chip is at least 25% smaller than the main surface of the MEMS chip.

Abstract translation: MEMS器件包括第一芯片和MEMS芯片。 第一芯片具有安装表面并且至少包括集成电路。 MEMS芯片具有主表面，在该主表面上布置有用于接触MEMS器件的第一组接触焊盘和用于接触第一芯片的第二组接触焊盘。 第一芯片通过面向主表面的安装表面机械地附接并电连接到第二组接触焊盘。 第一芯片的安装表面比MEMS芯片的主表面小至少25％。

公开(公告)号：US20140151701A1

公开(公告)日：2014-06-05

申请号：US13705367

申请日：2012-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward Fuergut ,  Horst Theuss ,  Walter Diez

IPC: H01L23/488 ,  H01L23/48 ,  H01L21/67 ,  H01L21/56 ,  H01L29/84

CPC classification number: H01L23/488 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/67242 ,  H01L23/48 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L29/84 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/82

Abstract: An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

Abstract translation: 提供嵌入式芯片封装。 嵌入式芯片封装包括多个芯片; 封装材料嵌入多个芯片; 电连接到所述多个芯片的至少一个电再分配层; 以及连接到所述至少一个电再分配层的公共终端，其中所述公共终端为所述多个芯片和所述公共终端之间的公共电信号的发射和接收中的至少一个提供接口。

公开(公告)号：US20230402423A1

公开(公告)日：2023-12-14

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11715719B2

公开(公告)日：2023-08-01

申请号：US16875531

申请日：2020-05-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/13 ,  H01L24/43 ,  H01L24/73

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US20220148934A1

公开(公告)日：2022-05-12

申请号：US17501568

申请日：2021-10-14

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Ralf Otremba ,  Daniel Pedone ,  Bernd Schmoelzer

IPC: H01L23/16 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.