公开(公告)号：US20230314703A1

公开(公告)日：2023-10-05

申请号：US17710690

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12007 ,  G02B6/136 ,  G02B6/29395

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and an opening is through the first substrate and the second substrate to expose a bottom surface of the MRR.

公开(公告)号：US20230207522A1

公开(公告)日：2023-06-29

申请号：US17561720

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin A. DESHPANDE ,  Ravindranath V. MAHAJAN

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L21/561 ,  H01L23/5389 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105

Abstract: Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.

公开(公告)号：US20230138543A1

公开(公告)日：2023-05-04

申请号：US18091982

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20210305132A1

公开(公告)日：2021-09-30

申请号：US16828405

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Digvijay RAORANE ,  Sairam AGRAHARAM ,  Nitin DESHPANDE ,  Mitul MODI ,  Manish DUBEY ,  Edvin CETEGEN

IPC: H01L23/482 ,  H01L23/538 ,  H01L23/495

Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

公开(公告)号：US20180358296A1

公开(公告)日：2018-12-13

申请号：US15778398

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Eric J. LI ,  Nitin DESHPANDE ,  Shawna M. LIFF ,  Omkar KARHADE ,  Amram EITAN ,  Timothy A. GOSSELIN

IPC: H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

公开(公告)号：US20230314850A1

公开(公告)日：2023-10-05

申请号：US17710716

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE ,  Tim Tri HOANG

IPC: G02F1/01 ,  G02B6/293

CPC classification number: G02F1/0147 ,  G02B6/29395 ,  G02F2203/15 ,  G02B6/2934

Abstract: Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

公开(公告)号：US20220199600A1

公开(公告)日：2022-06-23

申请号：US17132976

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Kemal AYGÜN ,  Suresh V. POTHUKUCHI ,  Xiaoqian LI ,  Omkar KARHADE

IPC: H01L25/18 ,  H01L25/00 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196940A1

公开(公告)日：2022-06-23

申请号：US17131654

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Xiaoqian LI ,  Nitin DESHPANDE ,  Sujit SHARAN

IPC: G02B6/42

Abstract: A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

公开(公告)号：US20220187548A1

公开(公告)日：2022-06-16

申请号：US17122340

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Divya PRATAP ,  Hiroki TANAKA ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Srinivas V. PIETAMBARAM ,  Xiaoqian LI ,  Sai VADLAMANI ,  Jeremy ECTON

IPC: G02B6/42 ,  G02F1/01 ,  G02F1/09

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.