公开(公告)号：US20080042290A1

公开(公告)日：2008-02-21

申请号：US11679723

申请日：2007-02-27

申请人： Jong-Myeong Lee ,  Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Kyung-In Choi ,  Hyun-Bae Lee

发明人： Jong-Myeong Lee ,  Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Won Hong ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC分类号： H01L23/522 ,  H01L21/311

CPC分类号： H01L21/76804 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

摘要翻译： 用于电连接铝和铜互连的结构和形成方法使用电连接铝和铜互连的内部形状来稳定半导体金属化工艺。 为此，铜互连设置在半导体衬底上。 互连感应层和互连插入层依次形成在铜互连上以具有暴露铜互连的接触孔。 接触孔的上直径可以形成为大于其直径。 阻挡层和铝互连填充在接触孔中。 铝互连形成为不通过接触孔直接接触铜互连。

公开(公告)号：US20100151672A1

公开(公告)日：2010-06-17

申请号：US12711812

申请日：2010-02-24

申请人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

发明人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

IPC分类号： H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer.

摘要翻译： 提供形成金属互连结构的方法。 所述方法包括在包括第一金属互连的半导体衬底上形成绝缘层。 图案化绝缘层以形成露出第一金属互连的开口。 在暴露的第一金属互连上形成第一扩散阻挡层。 在形成第一扩散阻挡层之后，在开口中的第一扩散阻挡层上形成第二扩散阻挡层，第二扩散阻挡层与开口的侧壁接触。 第二金属互连形成在第二扩散阻挡层上。

公开(公告)号：US08124524B2

公开(公告)日：2012-02-28

申请号：US12711812

申请日：2010-02-24

申请人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

发明人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer.

摘要翻译： 提供形成金属互连结构的方法。 所述方法包括在包括第一金属互连的半导体衬底上形成绝缘层。 图案化绝缘层以形成露出第一金属互连的开口。 在暴露的第一金属互连上形成第一扩散阻挡层。 在形成第一扩散阻挡层之后，在开口中的第一扩散阻挡层上形成第二扩散阻挡层，第二扩散阻挡层与开口的侧壁接触。 第二金属互连形成在第二扩散阻挡层上。

公开(公告)号：US20090011583A1

公开(公告)日：2009-01-08

申请号：US12165805

申请日：2008-07-01

申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

IPC分类号： H01L21/28

CPC分类号： H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

摘要： A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

摘要翻译： 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。

公开(公告)号：US07972941B2

公开(公告)日：2011-07-05

申请号：US12165805

申请日：2008-07-01

申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

IPC分类号： H01L21/322

CPC分类号： H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

摘要： A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

摘要翻译： 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。

公开(公告)号：US20090176124A1

公开(公告)日：2009-07-09

申请号：US12291069

申请日：2008-11-05

申请人： Jong-Won Hong ,  Min-Keun Kwak ,  Geum-Jung Seong ,  Jong-Myeong Lee ,  Gil-Heyun Choi ,  Hong-Kyu Hwang

发明人： Jong-Won Hong ,  Min-Keun Kwak ,  Geum-Jung Seong ,  Jong-Myeong Lee ,  Gil-Heyun Choi ,  Hong-Kyu Hwang

IPC分类号： H01L29/12 ,  B32B15/01 ,  B32B15/04

CPC分类号： B32B15/01 ,  B32B15/017 ,  B32B15/018 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05181 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/15311 ,  H01L2924/3025 ,  Y10T428/12528 ,  Y10T428/12701 ,  Y10T428/12736 ,  Y10T428/12882 ,  Y10T428/12896 ,  Y10T428/12931 ,  Y10T428/31678 ,  H01L2224/05552

摘要： A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device.

摘要翻译： 用于半导体器件的焊盘结构包括在器件的接合区域中的第二上金属层下面的第一下金属层。 下金属层形成为使得下金属层的金属不存在于接合区域中。 结果，如果在诸如在接合区域处的探测或接合的过程中结构发生损坏，则下部金属不暴露于环境中。 通过暴露于环境来防止下层金属层的氧化，从而提高了装置的可靠性。

公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US07759248B2

公开(公告)日：2010-07-20

申请号：US11585087

申请日：2006-10-24

申请人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jong-Won Hong ,  Seung-Gil Yang ,  Kyung-In Choi ,  Hyun-Bae Lee

发明人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jong-Won Hong ,  Seung-Gil Yang ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/76843

摘要： A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.

摘要翻译： 公开了一种半导体存储器件及其制造方法。 半导体存储器件可以包括掺杂有杂质的导电层，在导电层上不掺杂的非导电层，在非导电层上的层间绝缘膜，并且具有用于暴露非导电层的上表面的接触孔 导电层，接触孔上的欧姆钨膜，渗透非导电层的欧姆钨膜的下部与导电层接触，在欧姆钨膜上的接触孔上形成氮化钨膜， 并在氮化钨膜上形成钨膜以填充接触孔。

公开(公告)号：US20070134914A1

公开(公告)日：2007-06-14

申请号：US11585087

申请日：2006-10-24

申请人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jong-Won Hong ,  Seung-Gil Yang ,  Kyung-In Choi ,  Hyun-Bae Lee

发明人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jong-Won Hong ,  Seung-Gil Yang ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/76843

摘要： A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.

摘要翻译： 公开了一种半导体存储器件及其制造方法。 半导体存储器件可以包括掺杂有杂质的导电层，在导电层上不掺杂的非导电层，在非导电层上的层间绝缘膜，并且具有用于暴露非导电层的上表面的接触孔 导电层，接触孔上的欧姆钨膜，渗透非导电层的欧姆钨膜的下部与导电层接触，在欧姆钨膜上的接触孔上形成氮化钨膜， 并在氮化钨膜上形成钨膜以填充接触孔。