公开(公告)号：US07211899B2

公开(公告)日：2007-05-01

申请号：US10336728

申请日：2003-01-06

申请人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

发明人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/15 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/4605 ,  H05K2201/09827 ,  H05K2203/025

摘要： A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.

摘要翻译： 电路基板包括玻璃基板16，通过玻璃基板16形成的通孔18和埋在通孔18中的通孔电极20。 通孔18的开口宽度在玻璃基板的内部是最小的，并且朝向玻璃基板16的两个表面增加。 因此，可以防止通孔电极20的分离，而不会增加通孔内壁的表面粗糙度，并且可以减轻芯基板中产生的应力。

公开(公告)号：US06768205B2

公开(公告)日：2004-07-27

申请号：US10084923

申请日：2002-03-01

申请人： Osamu Taniguchi ,  Tomoko Miyashita ,  Yasuo Yamagishi ,  Koji Omote ,  Yoshihiko Imanaka

发明人： Osamu Taniguchi ,  Tomoko Miyashita ,  Yasuo Yamagishi ,  Koji Omote ,  Yoshihiko Imanaka

IPC分类号： H01L2713

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13009 ,  H01L2224/16 ,  H01L2224/73257 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.

摘要翻译： 本发明的目的是提供一种可靠的薄膜电路衬底或通孔形成的衬底，其以细间距设置有微通孔塞。 该目的通过在Si衬底上形成用作蚀刻阻挡层的绝缘层，然后使用半导体工艺在Si衬底中形成通孔，直到暴露出蚀刻阻挡层。 此外，在绝缘层上形成薄膜电路，并且在通孔处去除绝缘层，使薄膜电路露出。 根据需要，对薄膜电路进行热处理，然后用导电材料填充通孔，并形成鞋面电极。

公开(公告)号：US06580169B2

公开(公告)日：2003-06-17

申请号：US10191533

申请日：2002-07-10

申请人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

发明人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

IPC分类号： H01L2348

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1532 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0266 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0574 ,  H05K2203/0577 ,  H05K2203/0769

摘要： The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.

公开(公告)号：US06504966B2

公开(公告)日：2003-01-07

申请号：US10077342

申请日：2002-02-15

申请人： Masayuki Kato ,  Akio Sugama ,  Koji Tsukamoto ,  Masatoshi Ishii ,  Kishio Yokouchi ,  Yasuo Yamagishi ,  Motoyuki Nishizawa ,  Tsuyoshi Aoki

发明人： Masayuki Kato ,  Akio Sugama ,  Koji Tsukamoto ,  Masatoshi Ishii ,  Kishio Yokouchi ,  Yasuo Yamagishi ,  Motoyuki Nishizawa ,  Tsuyoshi Aoki

IPC分类号： G02B626

CPC分类号： G02F1/295 ,  G02B6/125 ,  G02B2006/12104 ,  G02B2006/12114 ,  G02B2006/12145 ,  G02F1/313

摘要： A prism pair is employed as an optical deflecting element. The prism pair is constructed by a slab waveguide, and first and second upper electrodes and first and second lower electrodes arranged on and under the slab waveguide. These electrodes are shaped into a wedge shape (e.g., triangular shape), and change the refractive index of a part of the slab waveguide by utilizing the electrooptic effect to change the propagation direction of light.

摘要翻译： 棱镜对被用作光学偏转元件。 棱镜对由平板波导构成，第一和第二上电极以及设置在平板波导上和下方的第一和第二下电极。 这些电极成形为楔形（例如，三角形），并且通过利用电光效应来改变平板波导的一部分的折射率以改变光的传播方向。

公开(公告)号：US5278684A

公开(公告)日：1994-01-11

申请号：US928767

申请日：1992-08-17

申请人： Akihiro Mochizuki ,  Fumiyo Onda ,  Toshiaki Yoshihara ,  Masayuki Iwasaki ,  Yasuo Yamagishi

发明人： Akihiro Mochizuki ,  Fumiyo Onda ,  Toshiaki Yoshihara ,  Masayuki Iwasaki ,  Yasuo Yamagishi

IPC分类号： G02F1/133 ,  G02F1/139 ,  G02F1/137

CPC分类号： G02F1/13306 ,  G02F1/1393

摘要： A liquid crystal display element comprising a liquid crystal composition having an optically active compound as at least one constituent and showing a cholesteric phase in a bulk state, wherein the liquid crystal composition is arranged between substrates, at least one of which is provided with a transparent electrode, so that long axes of individual liquid crystal molecules are in parallel to one another and are oriented in the same direction as the surfaces of the substrates, and the long axes of the molecules are uniformly aligned in parallel, vertically or inclined to the surfaces of the substrates, wherein the gap d (.mu.m) between the substrates and the size p (.mu.m) of the helical pitch shown by the cholesteric phase liquid crystal at room temperature when an electric field is not applied satisfy the following relationships:d/p.gtoreq. 1.

摘要翻译： 一种液晶显示元件，包括具有至少一种组分的光学活性化合物并显示出大量状态的胆甾醇相的液晶组合物，其中所述液晶组合物布置在基板之间，其中至少一个具有透明 电极，使得各个液晶分子的长轴彼此平行并且沿与基板的表面相同的方向取向，并且分子的长轴在平行，垂直或相对于表面的方向上均匀排列 的基底，其中当不施加电场时，在室温下由胆甾型相液晶所示的螺旋音调的间距d（（my）m）和尺寸p（（my）m）满足 以下关系：d / p> = 1。

公开(公告)号：US07678695B2

公开(公告)日：2010-03-16

申请号：US11714777

申请日：2007-03-07

申请人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

发明人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/15 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/4605 ,  H05K2201/09827 ,  H05K2203/025

摘要： A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.

摘要翻译： 电路基板包括玻璃基板16，通过玻璃基板16形成的通孔18和埋在通孔18中的通孔电极20.通孔18的开口宽度在玻璃基板的内部最小，并且朝向 因此，可以防止通孔电极20的脱离，而不增加通孔内壁的表面粗糙度，并且可以减轻在芯基板中产生的应力。

公开(公告)号：US07595228B2

公开(公告)日：2009-09-29

申请号：US11233177

申请日：2005-09-23

申请人： Tomoyuki Abe ,  Yasuo Yamagishi

发明人： Tomoyuki Abe ,  Yasuo Yamagishi

IPC分类号： H01L21/70 ,  H01L21/98

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/10165 ,  H01L2224/1182 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73203 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K3/3436 ,  H05K3/3489 ,  H05K3/3494 ,  H05K3/4682 ,  H05K2203/0475 ,  H05K2203/111 ,  Y02P70/613 ,  H01L2224/0401

摘要： A method for manufacturing an electronic component-mounted board (X) includes a temperature raising step for heating an electronic component (30A), with a solder bump electrode (31) containing a solder material, to a first temperature higher than the melting point of the solder material, while also heating a wiring board (X′), with an electrode section (21) corresponding to the solder bump electrode (31), to a second temperature lower than the first temperature. The method further includes a joining step for joining the solder bump electrode (31) and the electrode section (21) by pressing the electronic component (30A) against the wiring board (X′), with the solder bump electrodes (31) and the electrode sections (21) abutting against each other.

摘要翻译： 一种电子部件安装板（X）的制造方法，包括：将包含焊料材料的焊料凸块电极（31）加热到高于熔点的第一温度的电子部件（30A）的升温工序， 焊料材料，同时将与焊料凸块电极（31）相对应的电极部分（21）加热到低于第一温度的第二温度的布线板（X'）。 该方法还包括通过用焊料凸块电极（31）和焊料凸块电极（31）将电子部件（30A）压靠在布线板（X'）上而将焊料凸块电极（31）和电极部分（21） 电极部分（21）彼此抵靠。

公开(公告)号：US07557014B2

公开(公告)日：2009-07-07

申请号：US11600211

申请日：2006-11-16

申请人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

发明人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011

摘要： A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

摘要翻译： 一种半导体装置，包括：支撑基板，其具有填充有适于第一间距的导体的通孔; 形成在所述支撑基板上或上方的电容器; 形成在所述支撑基板上或上方的布线层，使一些所述通孔向上填充有通过所述电容器的导体，具有分支，并且具有不同于所述第一间距的第二间距的导线; 以及设置在所述布线层上或上方的多个半导体元件，具有适于所述第二间距的端子，并且经由所述端子与所述布线层连接。 其中具有窄端子间距的半导体元件，具有较宽节距的导线的支撑件和电容器的半导体装置被适当地电连接以实现具有减小的电感和大电容的去耦功能。

公开(公告)号：US07351361B2

公开(公告)日：2008-04-01

申请号：US11232012

申请日：2005-09-22

申请人： Kozo Shimizu ,  Yasuo Yamagishi

发明人： Kozo Shimizu ,  Yasuo Yamagishi

IPC分类号： H01B1/02 ,  H01B1/22

CPC分类号： H01B1/22 ,  H01B1/02 ,  H01C7/005 ,  H01C7/008 ,  H01C17/06526 ,  H01C17/06586 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01322 ,  H05K3/321 ,  H05K3/3484 ,  H05K2201/0218 ,  H05K2203/0425 ,  Y10T428/2982 ,  Y10T428/2991

摘要： A conductive composition layer, conductive particles as a raw material, a conductive composition therefor, a manufacturing method of the conductive composition layer, etc. are provided wherewith heat conductance can be accelerated between electronic devices or electronic devices can be electrically connected. The conductive composition layer is formed by subjecting to heat treatment at a temperature lower than 230° C. a conductive composition comprising conductive particles having a metal base material and a metal coating material thereon as well as a thermosetting resin having a curing temperature that is lower than 230° C. and/or a thermoplastic resin having a melting point that is lower than 230° C.

摘要翻译： 提供导电组合物层，作为原料的导电颗粒，其导电组合物，导电组合物层的制造方法等，可以在电子装置或电子装置之间电连接热传导。 导电组合物层通过在低于230℃的温度下进行热处理而形成，导电组合物包含其上具有金属基材和金属涂层材料的导电颗粒以及固化温度较低的热固性树脂 超过230℃，和/或熔点低于230℃的热塑性树脂。

公开(公告)号：US20070065981A1

公开(公告)日：2007-03-22

申请号：US11600211

申请日：2006-11-16

申请人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

发明人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011

摘要： A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.