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    Process for fabricating high-density mask ROM devices
    11.
    发明授权
    Process for fabricating high-density mask ROM devices 失效
    制造高密度掩模ROM器件的工艺

    公开(公告)号：US5504030A

    公开(公告)日：1996-04-02

    申请号：US505050

    申请日：1995-07-21

    Applicant: Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

    Inventor： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

    IPC: H01L21/8246

    CPC classification number: H01L27/11246 ,  Y10S438/981

    Abstract: A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

    Abstract translation: 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。

    Electrostatic discharge (ESD) protection device
    12.
    发明授权
    Electrostatic discharge (ESD) protection device 有权
    静电放电（ESD）保护装置

    公开(公告)号：US08817434B2

    公开(公告)日：2014-08-26

    申请号：US13270298

    申请日：2011-10-11

    Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H02H9/00

    CPC classification number: H02H9/00 ,  H01L27/0266

    Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

    Abstract translation: 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。

    Method for evaluating failure rate
    13.
    发明授权
    Method for evaluating failure rate 有权
    评估失败率的方法

    公开(公告)号：US08510635B2

    公开(公告)日：2013-08-13

    申请号：US12979914

    申请日：2010-12-28

    Applicant: Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    Inventor： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    IPC: G11C29/00

    CPC classification number: G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

    Abstract translation: 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

    ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE
    16.
    发明申请
    ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE 有权
    静电放电（ESD）器件和半导体结构

    公开(公告)号：US20130113045A1

    公开(公告)日：2013-05-09

    申请号：US13290399

    申请日：2011-11-07

    Applicant: Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

    Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

    Abstract translation: 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

    ESD protection circuit and ESD protection device thereof
    17.
    发明申请
    ESD protection circuit and ESD protection device thereof 有权
    ESD保护电路及其ESD保护装置

    公开(公告)号：US20120170160A1

    公开(公告)日：2012-07-05

    申请号：US12981521

    申请日：2010-12-30

    Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H02H9/00

    CPC classification number: H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

    Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

    Abstract translation: ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

    Method for fabricating a test structure
    18.
    发明授权
    Method for fabricating a test structure 失效
    制造测试结构的方法

    公开(公告)号：US07759957B2

    公开(公告)日：2010-07-20

    申请号：US11829104

    申请日：2007-07-27

    Applicant: Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    Inventor： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    IPC: G01R31/02 ,  H01L21/66

    CPC classification number: G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a test structure, in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

    Abstract translation: 一种用于制造测试结构的方法，其中在晶片上形成加热板，用于加热位于加热板上方或附近的待测试结构。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    19.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090278170A1

    公开(公告)日：2009-11-12

    申请号：US12116231

    申请日：2008-05-07

    Applicant: Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

    Inventor： Yun-Chi Yang ,  Jih-Shun Chiang ,  Cheng-Li Lin ,  Ju-Ping Chen ,  Kuan-Cheng Su

    IPC: H01L29/778 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/3148 ,  H01L29/456 ,  H01L29/665

    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having at least a gate structure formed thereon, forming LDDs in the substrate respectively at two side of the gate structure and a spacer at sidewalls of the gate structure, forming a source/drain in the substrate at two side of the gate structure, performing ant etching process to form recesses respectively in the source/drain, forming a barrier layer in the recesses; and performing a salicide process.

    Abstract translation: 一种制造半导体器件的方法包括提供至少形成有栅极结构的衬底，分别在栅极结构的两侧在衬底中形成LDD，在栅极结构的侧壁形成间隔物，在栅极结构的侧壁形成源极/漏极 基板在栅极结构的两侧，进行蚂蚁蚀刻处理以分别在源极/漏极中形成凹槽，在凹部中形成阻挡层; 并执行自杀过程。

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