公开(公告)号：US20200168572A1

公开(公告)日：2020-05-28

申请号：US16779217

申请日：2020-01-31

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang ,  Che-Ya Chou

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/16

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

公开(公告)号：US20200091070A1

公开(公告)日：2020-03-19

申请号：US16430076

申请日：2019-06-03

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US10483211B2

公开(公告)日：2019-11-19

申请号：US15418896

申请日：2017-01-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Nai-Wei Liu ,  Wei-Che Huang

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

公开(公告)号：US10217724B2

公开(公告)日：2019-02-26

申请号：US15047980

申请日：2016-02-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H05K1/18

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

公开(公告)号：US09899261B2

公开(公告)日：2018-02-20

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US09640505B2

公开(公告)日：2017-05-02

申请号：US14825443

申请日：2015-08-13

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

公开(公告)号：US20160307863A1

公开(公告)日：2016-10-20

申请号：US15189369

申请日：2016-06-22

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Tai-Yu Chen

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/18161 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括具有中心区域和围绕中心区域的周边区域的半导体管芯。 第一导电凸块设置在中心区域的半导体管芯上。 第二导电凸块设置在周边区域的半导体管芯上。 从顶视图看，第一导电凸块与第二导电凸块的面积比大于1，小于或等于3。

公开(公告)号：US20160211318A1

公开(公告)日：2016-07-21

申请号：US14925995

申请日：2015-10-29

Applicant: MEDIATEK INC.

Inventor： Chao-Yang Yeh ,  Chee-Kong Ung ,  Tzu-Hung Lin ,  Jia-Wei Fang

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L28/40 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/16 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/014

Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.

Abstract translation: 微电子封装包括具有芯片安装表面的封装衬底; 芯片安装在封装基板的芯片安装表面上，芯片的有源表面朝向芯片安装表面; 分布在芯片的有源表面上的多个输入/输出（I / O）焊盘; 以及安装在芯片的有源表面上的分立无源元件。 分立无源元件可以是去耦电容器，电阻器或电感器。

公开(公告)号：US08859340B2

公开(公告)日：2014-10-14

申请号：US14154564

申请日：2014-01-14

Applicant: MediaTek Inc.

Inventor： Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/52 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.

Abstract translation: 一种方法包括执行第一各向异性蚀刻工艺以从金属片的顶表面去除金属片的一部分的操作，从而在金属片中形成多个第一凹槽; 将载体安装在金属板的顶表面上，覆盖第一凹槽; 执行第二各向异性蚀刻工艺以从所述金属片的底表面去除所述第一凹部下方的所述金属片的一部分; 从金属板的底面填充成型材料，使金属板的底面露出; 在所述金属板的顶表面上形成钝化层，具有穿过其中的多个开口; 通过所述开口形成多个第一金属通孔; 并在钝化层上形成焊接掩模层，使第一金属通孔露出。

公开(公告)号：US11948895B2

公开(公告)日：2024-04-02

申请号：US17810625

申请日：2022-07-04

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/043 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/043 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/5385 ,  H01L2224/16227

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.