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54 条记录 (耗时 0.031 秒)

    Non-repeated and non-uniform width seal ring structure
    11.
    发明授权
    Non-repeated and non-uniform width seal ring structure 有权
    不重复和不均匀的宽度密封环结构

    公开(公告)号：US07265436B2

    公开(公告)日：2007-09-04

    申请号：US10780512

    申请日：2004-02-17

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

    IPC分类号： H01L23/544

    CPC分类号： H01L23/564 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.

    摘要翻译： 描述形成改进的密封环结构的方法。 沿着模具的周边形成连续的金属密封环，其中金属密封环平行于模具的边缘并在模具的拐角处倾斜，以便不具有尖角，并且其中金属密封环具有 角部处的第一宽度和沿着边缘的第二宽度，其中第一宽度宽于第二宽度。

    Non-repeated and non-uniform width seal ring structure
    14.
    发明申请
    Non-repeated and non-uniform width seal ring structure 有权
    不重复和不均匀的宽度密封环结构

    公开(公告)号：US20050179213A1

    公开(公告)日：2005-08-18

    申请号：US10780512

    申请日：2004-02-17

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi

    IPC分类号： F16L21/04 ,  H01L23/00 ,  H01L23/58

    CPC分类号： H01L23/564 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an improved seal ring structure is described. A continuous metal seal ring is formed along a perimeter of a die wherein the metal seal ring is parallel to the edges of the die and sloped at the corner of the die so as not to have a sharp corner and wherein the metal seal ring has a first width at the corners and a second width along the edges wherein the first width is wider than the second width.

    摘要翻译： 描述形成改进的密封环结构的方法。 沿着模具的周边形成连续的金属密封环，其中金属密封环平行于模具的边缘并在模具的拐角处倾斜，以便不具有尖角，并且其中金属密封环具有 角部处的第一宽度和沿着边缘的第二宽度，其中第一宽度宽于第二宽度。

    Test patterns for measurement of effective vacancy diffusion area
    15.
    发明申请
    Test patterns for measurement of effective vacancy diffusion area 失效
    用于测量有效空位扩散面积的测试模式

    公开(公告)号：US20050139827A1

    公开(公告)日：2005-06-30

    申请号：US11018604

    申请日：2004-12-21

    申请人： Chih-Hsiang Yao ,  Tai-Chun Huang

    发明人： Chih-Hsiang Yao ,  Tai-Chun Huang

    IPC分类号： H01L23/544 ,  H01L29/00

    CPC分类号： H01L22/34

    摘要： A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

    摘要翻译： 测试图案（100,200,300,400,600,700）具有设置在基底（352）上的第一金属结构（102），设置在第一金属结构（102）上方的一个或多个中间层（358）和 设置在所述一个或多个中间层（352）上方的第二金属结构（104）。 第一通孔（106）穿过中间层（352）并将第一金属结构（102）连接到第二金属结构（104）。 一个或多个第三金属结构（108）设置在一个或多个中间层（352）和第一金属结构（102）上方。 一个或多个第二通孔（110）穿过中间层（352）并将第一金属结构（102）连接到第三金属结构（108）。 第二通路（110）位于距离第一通孔（106）的中心的半径（R）的外侧。 第三金属结构（110）通过介电材料（366）与第二金属结构（104）分离。

    Integration film scheme for copper / low-k interconnect
    16.
    发明申请
    Integration film scheme for copper / low-k interconnect 有权
    铜/低k互连的集成电路方案

    公开(公告)号：US20050098896A1

    公开(公告)日：2005-05-12

    申请号：US10706156

    申请日：2003-11-12

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    IPC分类号： H01L23/532 ,  H01L23/48

    CPC分类号： H01L23/53295 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.

    摘要翻译： 用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。 第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。 第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。 第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件 。

    Method and pattern for reducing interconnect failures
    17.
    发明授权
    Method and pattern for reducing interconnect failures 有权
    减少互连故障的方法和模式

    公开(公告)号：US06831365B1

    公开(公告)日：2004-12-14

    申请号：US10448656

    申请日：2003-05-30

    申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

    发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

    IPC分类号： H01L2348

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

    摘要翻译： 描述了用于减少互连故障的方法和模式。 该方法和图案用于金属/电介质/金属的多层结构。 至少一个辅助图案附着到多层结构的一个金属层。 由辅助图案产生的热应力梯度可以收集金属层的空位，以防止应力诱导的空隙在连接两个金属层的通孔塞的底部产生。

    Semiconductor device fault detection system and method
    18.
    发明授权
    Semiconductor device fault detection system and method 有权
    半导体器件故障检测系统及方法

    公开(公告)号：US07791070B2

    公开(公告)日：2010-09-07

    申请号：US11264911

    申请日：2005-11-02

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

    IPC分类号： G01R31/26

    CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

    摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。