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公开(公告)号：US20190259780A1
公开(公告)日：2019-08-22
申请号：US16402713
申请日：2019-05-03
发明人： Shiqun GU , Daniel Daeik KIM , Matthew Michael NOWAK , Jonghae KIM , Changhan Hobie YUN , Je-Hsiung Jeffrey LAN , David Francis BERDY
IPC分类号： H01L27/12 , H01L23/498 , H01L21/306 , H01L23/66 , H01L27/088 , H01L21/304 , H01L21/8234 , H01L21/84 , H01L29/10 , H01L27/092 , H01L21/762 , H01L21/768 , H01L23/528
摘要： An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.
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公开(公告)号：US20180047660A1
公开(公告)日：2018-02-15
申请号：US15233906
申请日：2016-08-10
发明人： Chengjie ZUO , Mario Francisco VELEZ , Changhan Hobie YUN , David Francis BERDY , Daeik Daniel KIM , Jonghae KIM
IPC分类号： H01L23/498 , H01L21/48 , H01L23/15 , H01L23/31 , H01L21/56
CPC分类号： H01L23/49805 , H01L21/4846 , H01L21/56 , H01L23/145 , H01L23/15 , H01L23/3121 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/645 , H01L24/02 , H05K1/0218 , H05K3/3436 , H05K2201/10719
摘要： A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.
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公开(公告)号：US20170372975A1
公开(公告)日：2017-12-28
申请号：US15191062
申请日：2016-06-23
发明人： Daeik Daniel KIM , David Francis BERDY , Changhan Hobie YUN , Mario Francisco VELEZ , Chengjie ZUO , Jonghae KIM
IPC分类号： H01L21/66 , H01L23/544 , H01L23/66
CPC分类号： H01L22/32 , H01L23/544 , H01L27/13 , H01L2223/5446 , H01L2223/54493 , H03H7/00 , H03H7/1766 , H03H7/1791 , H03H7/463 , H03H2001/0078 , H04B1/0057
摘要： A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric layer supported by the die. The RF integrated circuit may also include an inline pad structure coupled to the at least one pair of capacitors proximate an edge of the die. The inline pad structure may include a first portion and a second portion extending into a dicing street toward the edge of the die and covered by at least a second dielectric layer.
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公开(公告)号：US20170338788A1
公开(公告)日：2017-11-23
申请号：US15161138
申请日：2016-05-20
发明人： Changhan Hobie YUN , David Francis BERDY , Chengjie ZUO , Daeik Daniel KIM , Jonghae KIM , Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE , Robert Paul MIKULKA
IPC分类号： H03H7/01 , H05K3/18 , H05K3/00 , H05K1/11 , H03H1/00 , H05K1/03 , H05K1/02 , H05K3/40 , H05K1/16
CPC分类号： H03H7/1758 , H01F5/003 , H01F41/04 , H01F41/041 , H01P1/203 , H01P1/2135 , H01P5/12 , H03H1/00 , H03H7/0115 , H03H7/09 , H03H7/1766 , H03H7/1775 , H03H7/463 , H03H2001/0078 , H05K1/0237 , H05K1/0306 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/186 , H05K3/0026 , H05K3/18 , H05K3/4038
摘要： The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.
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公开(公告)号：US20170200550A1
公开(公告)日：2017-07-13
申请号：US14991803
申请日：2016-01-08
CPC分类号： H01F27/2804 , H01F17/0013 , H01F41/041 , H01L23/5222 , H01L23/5227 , H01L27/0207 , H01L28/10 , H04B1/40
摘要： A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.
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公开(公告)号：US20170077093A1
公开(公告)日：2017-03-16
申请号：US15298124
申请日：2016-10-19
发明人： Daeik Daniel KIM , David Francis BERDY , Je-Hsiung Jeffrey LAN , Changhan Hobie YUN , Jonghae KIM
CPC分类号： H01L27/0808 , H01L21/7624 , H01L21/76264 , H01L21/78 , H01L27/1203 , H01L29/66174 , H01L29/66181 , H01L29/93
摘要： A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.
摘要翻译： 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极，作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外，掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。
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公开(公告)号：US20160020013A1
公开(公告)日：2016-01-21
申请号：US14335609
申请日：2014-07-18
发明人： David Francis BERDY , Chengjie ZUO , Daeik Daniel KIM , Changhan Hobie YUN , Mario Francisco VELEZ , Robert Paul MIKULKA , Jonghae KIM
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F27/29 , H01F2017/004 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
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公开(公告)号：US20170372831A1
公开(公告)日：2017-12-28
申请号：US15192802
申请日：2016-06-24
发明人： Mario Francisco VELEZ , Daeik Daniel KIM , Niranjan Sunil MUDAKATTE , David Francis BERDY , Changhan Hobie YUN , Jonghae KIM , Chengjie ZUO , Yunfei MA , Robert Paul MIKULKA
CPC分类号： H01F41/041 , H01F17/0013 , H01F17/0033 , H01F2017/002 , H01L23/3128 , H01L23/645 , H01L24/19 , H01L24/24 , H01L24/96 , H01L2224/023 , H01L2224/12105 , H01L2224/24195 , H01L2924/1206 , H01L2924/18162 , H01L2924/19042 , H01L2924/19105
摘要： Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.
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公开(公告)号：US20170221846A1
公开(公告)日：2017-08-03
申请号：US15077869
申请日：2016-03-22
发明人： Daeik Daniel KIM , Mario Francisco VELEZ , Changhan Hobie YUN , Chengjie ZUO , David Francis BERDY , Jonghae KIM , Niranjan Sunil MUDAKATTE
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L23/15 , H01L23/3171 , H01L23/3192 , H01L23/49816 , H01L24/14 , H01L2224/11003 , H01L2224/11005 , H01L2224/1148 , H01L2224/1405 , H01L2224/14104 , H01L2224/145 , H05K1/0306 , H05K1/111 , H05K3/0052 , H05K2201/0154 , H05K2201/0195 , H05K2201/09845 , Y02P70/611
摘要： A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
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公开(公告)号：US20170133148A1
公开(公告)日：2017-05-11
申请号：US15345312
申请日：2016-11-07
发明人： Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE , Changhan Hobie YUN , Daeik Daniel KIM , David Francis BERDY , Jonghae KIM , Yunfei MA , Chengjie ZUO
IPC分类号： H01F27/28 , H01L23/00 , H01L21/56 , H01F38/14 , H01F27/02 , H01F27/29 , H01F41/06 , H01L23/31 , H04B5/00
CPC分类号： H01F27/2823 , H01F27/022 , H01F27/2828 , H01F27/29 , H01F38/14 , H01F41/06 , H01L21/565 , H01L23/3107 , H01L23/3157 , H01L23/5227 , H01L23/645 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L28/00 , H01L28/10 , H01L2223/6677 , H01L2224/0401 , H01L2224/04042 , H01L2224/08265 , H01L2224/16227 , H01L2224/45015 , H01L2224/45147 , H01L2224/4813 , H01L2224/73257 , H01L2924/00014 , H01L2924/15311 , H01L2924/16235 , H01L2924/19042 , H01L2924/19104 , H04B5/0037 , H04B5/0081 , H01L2224/05599 , H01L2924/20751 , H01L2224/85399
摘要： An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.
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