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公开(公告)号:US20170062021A1
公开(公告)日:2017-03-02
申请号:US15351600
申请日:2016-11-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takafumi BETSUI , Naoto TAOKA , Motoo SUWA , Shigezumi MATSUI , Norihiko SUGITA , Yoshiharu FUKUSHIMA
IPC: G11C5/04
CPC classification number: G11C5/04 , G11C5/02 , G11C5/06 , G11C5/063 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L25/18 , H01L2224/16 , H01L2224/16227 , H01L2224/49175 , H01L2924/1432 , H01L2924/14361 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H05K1/0237 , H05K1/181 , H05K3/4602 , H05K2201/09236 , H05K2201/093 , H05K2201/09663 , H05K2201/10159 , H05K2201/10522 , H05K2201/10734 , Y02P70/611 , H01L2924/00
Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下,与仅在一侧具有存储器接口电路的半导体板相比,可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此,微型计算机在主板和模块板上简化了线路设计。
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公开(公告)号:US20170032834A1
公开(公告)日:2017-02-02
申请号:US15170535
申请日:2016-06-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Motoo SUWA , Takafumi BETSUI , Masato SUZUKI
IPC: G11C11/408 , H01L25/065 , G11C5/06 , H01L23/528 , G11C5/02 , H01L23/498 , H01L23/522
CPC classification number: G11C5/063 , G11C5/025 , G11C11/4082 , G11C11/4093 , G11C2207/105 , H01L23/5228 , H01L23/5283 , H01L23/5386 , H01L23/647 , H01L25/0655 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.
Abstract translation: 包括在包括在电子设备中的半导体器件中的终端的数量减少。 电子设备包括:具有第一和第二输入端的第一半导体器件; 具有第一输出端和驱动所述第一输出端的第一驱动电路的第二半导体器件; 以及安装有第一和第二半导体器件的布线基板。 第一和第二输入端通常经由形成在布线基板上的第一线耦合到第一输出端。 分别耦合到第一和第二输入端的第一和第二终端电阻的复合电阻值等于第一驱动电路的驱动阻抗。
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公开(公告)号:US20230369257A1
公开(公告)日:2023-11-16
申请号:US17743033
申请日:2022-05-12
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yoshikazu TANAKA , Tadashi KAMEYAMA , Takafumi BETSUI
CPC classification number: H01L23/66 , H01P3/081 , H01L2223/6627 , H01L2223/6638
Abstract: A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.
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公开(公告)号:US20170354038A1
公开(公告)日:2017-12-07
申请号:US15480353
申请日:2017-04-05
Applicant: Renesas Electronics Corporation
Inventor: Takafumi BETSUI
IPC: H05K1/18 , H05K1/02 , H01L23/495 , H05K3/46 , H05K3/30
CPC classification number: H05K1/182 , H01L23/36 , H01L23/42 , H01L23/49589 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2224/16225 , H01L2924/15311 , H01L2924/3511 , H05K1/0231 , H05K1/0233 , H05K1/0234 , H05K1/183 , H05K1/185 , H05K3/301 , H05K3/429 , H05K3/4611 , H05K3/4697
Abstract: A semiconductor integrated circuit device (101) includes a component built-in board (21) in which at least a first core layer (Co21) on which a first electronic component (C21) is mounted, a second core layer (Co22) on which a second electronic component (C22) is mounted, an adhesive layer (Ad21) arranged between the first core layer (Co21) and the second core layer (Co22), and wiring layers (L21-L28) are stacked; a third electronic component (SoC) mounted in a first core layer (Co21) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22) through the wiring layers (L21 to L28); and an external connection terminal (BE) formed in a second core layer (Co22) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22).
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公开(公告)号:US20170062322A1
公开(公告)日:2017-03-02
申请号:US15207559
申请日:2016-07-12
Applicant: Renesas Electronics Corporation
Inventor: Kazuyuki SAKATA , Takafumi BETSUI
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/563 , H01L22/32 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/06133 , H01L2224/06136 , H01L2224/06155 , H01L2224/06177 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/14133 , H01L2224/14136 , H01L2224/14155 , H01L2224/16238 , H01L2224/32245 , H01L2224/48227 , H01L2224/49173 , H01L2224/49175 , H01L2224/49179 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/014 , H01L2224/45099
Abstract: A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.
Abstract translation: 具有增强可靠性的半导体器件。 半导体器件具有布线基板,其包括与半导体芯片的电源电位供给部电连接的第一端子,将电源电位供给部与第一端子连接的第一布线,与基准电位电连接的第二端子 半导体芯片的供电部分和将参考电位供应部分与第二端子耦合的第二布线。 第一端子和第二端子比半导体芯片更靠近布线基板的周边布置。 第二个接线沿着第一个接线延伸。
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公开(公告)号:US20170033045A1
公开(公告)日:2017-02-02
申请号:US15163647
申请日:2016-05-24
Applicant: Renesas Electronics Corporation
Inventor: Takafumi BETSUI , Nobuyuki MORIKOSHI , Tetsushi HADA
IPC: H01L23/522 , G06F13/42 , G06F1/32 , H01L23/00 , H01L23/498
CPC classification number: H01L23/5227 , G06F1/3243 , G06F1/3296 , G06F13/385 , G06F13/4282 , H01L23/49838 , H01L24/16 , H01L2224/16227 , H01L2224/1623 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01R13/6456 , H01R24/58
Abstract: Object is to provide a semiconductor device with fewer malfunctions. The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals. When viewed from the second main surface, second external terminals to be supplied with the first signal and the second signal are arranged closer to the semiconductor chip than second external terminals to be supplied with the first power supply voltage and the second power supply voltage.
Abstract translation: 目的是提供具有更少故障的半导体器件。 半导体器件具有半导体芯片,具有以第一电源电压工作的第一信号输出电路,以第二电源电压工作的第二信号输出电路和多个凸块电极; 以及布线基板,其具有与所述半导体芯片的主面相对的第一主面,与所述第一主面相对的第二主面,在所述第一主面之间具有布线层,所述第一主面与所述第一主面的第一外部端子, 表面; 前者安装在后者上以将凸块电极耦合到第一外部端子。 当从第二主表面观察时,被提供有第一信号的第二外部端子和第二信号被布置成比第二外部端子更靠近半导体芯片以被提供第一电源电压和第二电源电压。
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公开(公告)号:US20170032832A1
公开(公告)日:2017-02-02
申请号:US15178091
申请日:2016-06-09
Applicant: Renesas Electronics Corporation
Inventor: Motoo SUWA , Takafumi BETSUI
IPC: G11C11/4076 , H01L23/498 , H01L27/108
CPC classification number: G11C11/4076 , G11C5/063 , H01L23/498 , H01L23/49816 , H01L23/49827 , H01L23/49844 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L27/108 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311
Abstract: To provide an electronic device capable of improving a signal quality.The electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.
Abstract translation: 电子设备包括半导体存储器件,半导体器件,被配置为访问存储在半导体存储器件中的数据;以及布线基板,其上安装有半导体存储器件和半导体器件。 布线基板包括通过第一和第二布线层将半导体器件与半导体存储器件的每个第一和第二数据端电连接的第一和第二数据布线。 第一布线层是比第二布线层更靠近半导体器件配置的布线层,并且第一数据端子比第二数据端子位于比半导体器件更远的位置。
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公开(公告)号:US20230361092A1
公开(公告)日:2023-11-09
申请号:US18351777
申请日:2023-07-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takafumi BETSUI
IPC: H01L25/16 , H01L23/538 , H02M3/155
CPC classification number: H01L25/16 , H01L23/5384 , H02M3/155 , H01L23/5386 , H02M1/44
Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).
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公开(公告)号:US20220375804A1
公开(公告)日:2022-11-24
申请号:US17326829
申请日:2021-05-21
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Yoichi ISOZUMI , Takafumi BETSUI , Shuuichi KARIYAZAKI
IPC: H01L21/66 , H01L25/065 , H01L23/64 , H01L23/538
Abstract: A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.
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公开(公告)号:US20180301172A1
公开(公告)日:2018-10-18
申请号:US16010770
申请日:2018-06-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takafumi BETSUI , Naoto TAOKA , Motoo SUWA , Shigezumi MATSUI , Norihiko SUGITA , Yoshiharu FUKUSHIMA
Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
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