公开(公告)号：US20070284737A1

公开(公告)日：2007-12-13

申请号：US11422795

申请日：2006-06-07

申请人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

发明人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

IPC分类号： H01L23/48

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/4338 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511

摘要： Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

摘要翻译： 提供热界面材料及其在包装中的使用方法。 在一个方面，提供一种热界面材料，其包括具有第一表面和与第一表面相对的第二表面的铟预制件，内部部分和外围边界。 铟预制件具有从周边边界向内部延伸的通道。 该通道使热通量在热循环期间释放。

公开(公告)号：US06446818B1

公开(公告)日：2002-09-10

申请号：US09636515

申请日：2000-08-10

申请人： Ajit M. Dubey ,  Raj N. Master ,  Ot Ong ,  C S Chan

发明人： Ajit M. Dubey ,  Raj N. Master ,  Ot Ong ,  C S Chan

IPC分类号： A47F700

CPC分类号： H01L21/67333 ,  H01L21/67028 ,  H01L2221/68313

摘要： A boat for cleaning semiconductor packages, including cleaning ball grid array packages in centrifugal cleaners. The boat includes a bottom plate with receptacles for receiving semiconductor packages and a top plate having through holes, where each through hole is smaller than the receptacle with which it corresponds in the bottom plate. An alignment mechanism ensures that the top plate is aligned with the bottom plate in a manner that results in each through hole being positioned directly over a respective one of the receptacles. An attachment mechanism releasably attaches the top plate to the bottom plate in a co-planar relationship that results in the presence of a vertical space between the two plates.

摘要翻译： 用于清洁半导体封装的船，包括清洁球栅阵列包装在离心清洁器中。 船包括具有用于接收半导体封装的插座的底板和具有通孔的顶板，其中每个通孔小于在底板中与其对应的插座。 对准机构确保顶板与底板对齐，使得每个通孔直接定位在相应的一个容器上。 附接机构以平行关系可释放地将顶板附接到底板，导致两个板之间存在垂直空间。

公开(公告)号：US06333210B1

公开(公告)日：2001-12-25

申请号：US09577675

申请日：2000-05-25

申请人： Ajit M. Dubey ,  Raj N. Master

发明人： Ajit M. Dubey ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/0269 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/613

摘要： A method of maintaining z-height of an integrated circuit component, such as a multi-chip module, a chip or a die, and of visualizing alignment of an integrated circuit package during positioning of an integrated circuit component, is disclosed. The method maintains the z-height of an integrated circuit component during a solder reflow step by applying high-melting solder balls to interconnect pads on the package substrate surface. Such high-melting solder balls, for instance 90 Pb/10 Sn, do not collapse at temperatures sufficient to accomplish reflowing. The high-melting solder balls also make convenient visualization marks for alignment of the package substrate on an integrated circuit component placement tool, such as a die placement tool. A package substrate bearing high-melting solder balls in a pre-determined pattern is easily aligned by an integrated circuit placement tool using machine vision. Use of high-melting solder balls as visualization marks obviates the need for screen-printing of fiducial marks on the package substrate surface.

摘要翻译： 公开了一种在集成电路部件的定位期间保持诸如多芯片模块，芯片或芯片的集成电路部件的z高度以及集成电路封装的可视化对准的方法。 该方法通过施加高熔点焊球以在封装衬底表面上互连焊盘来在焊料回流步骤期间保持集成电路部件的z高度。 这种高熔点焊球，例如90 Pb / 10 Sn，在足以完成回流的温度下不会塌陷。 高熔点焊球还使得集成电路部件放置工具（例如管芯放置工具）上的封装基板对准的便利的可视标记。 通过使用机器视觉的集成电路放置工具容易地对准以预定图案承载高熔点焊球的封装衬底。 使用高熔点焊球作为可视化标记避免了在封装衬底表面上对基准标记进行丝网印刷的需要。

公开(公告)号：US6098867A

公开(公告)日：2000-08-08

申请号：US40511

申请日：1998-03-17

申请人： Raj N. Master ,  Maria G. Guardado ,  Mohammad Zubair Khan

发明人： Raj N. Master ,  Maria G. Guardado ,  Mohammad Zubair Khan

IPC分类号： H01L21/60 ,  H01L21/48 ,  B23K1/00 ,  B23K1/20 ,  B23K31/02

CPC分类号： H01L21/4864

摘要： An automated method of applying flux to substrate on which a semiconductor chip is to be assembled in a flip chip configuration by applying a controlled amount of flux to the substrate by a brush that applies the flux to the substrate in a programmed pattern of strokes thereby overcoming the surface tension of the flux/substrate surface. The programmed pattern of brush strokes is determined empirically for the specific combination of substrate and chip that is being assembled and is thus repeatable and operator independent. The empirically determined program also determines the amount of flux that will be applied to the substrate for the specific combination of substrate and chip being assembled. The empirically determined program is applied to a mechanical stage that moves the brush and to a flux reservoir by a CPU.

摘要翻译： 一种自动化方法，其通过将刷子施加受控量的通量施加到衬底上，以编程的行程模式将焊剂施加到衬底上，从而将焊剂施加到以半导体芯片组装的半导体芯片组装的衬底上，从而克服 助焊剂/基材表面的表面张力。 根据经验来确定编程的画笔笔画样式，用于正在组装的衬底和芯片的特定组合，并因此可重复且与操作者无关。 经验确定的程序还确定将被组装的衬底和芯片的特定组合将施加到衬底的通量的量。 经验确定的程序应用于通过CPU移动刷子和通量储存器的机械平台。

公开(公告)号：US07651938B2

公开(公告)日：2010-01-26

申请号：US11422795

申请日：2006-06-07

申请人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

发明人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

IPC分类号： H01L21/44 ,  H01L23/12

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/4338 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511

摘要： Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

摘要翻译： 提供热界面材料及其在包装中的使用方法。 在一个方面，提供一种热界面材料，其包括具有第一表面和与第一表面相对的第二表面的铟预制件，内部部分和外围边界。 铟预制件具有从周边边界向内部延伸的通道。 该通道使热通量在热循环期间释放。

公开(公告)号：US07601612B1

公开(公告)日：2009-10-13

申请号：US11255971

申请日：2005-10-24

申请人： Raj N. Master ,  Junaida A. Bakar ,  Diong H. Ding ,  Srinivasan Parthasarathy

发明人： Raj N. Master ,  Junaida A. Bakar ,  Diong H. Ding ,  Srinivasan Parthasarathy

IPC分类号： H01L21/00

CPC分类号： H05K3/3436 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/3463 ,  H05K3/3494 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05599

摘要： A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.

摘要翻译： 用于形成具有分散的Sn微结构的封装布置的焊接接头的方法在封装上提供了倒装芯片，其中倒装芯片具有通过共晶焊点连接到封装上的焊盘的焊料凸块。 共晶焊料在具有共晶回流曲线的焊料凸块/焊盘界面处回流，其被配置为实现具有基本上均匀分布的Sn晶粒的共晶焊点。 共晶回流曲线包括增加的冷却速率和降低的保持时间，并具有较高的峰值温度。 提供了焊接掩模中的焊盘开口与凸块下金属的限定比例。 共晶回流型材和定义的比例延长了包装布置中的疲劳寿命。

公开(公告)号：US07215030B2

公开(公告)日：2007-05-08

申请号：US11167425

申请日：2005-06-27

申请人： Raj N. Master ,  Srinivasan Ashok Anand ,  Srinivasan Parthasarathy ,  Yew Cheong Mui

发明人： Raj N. Master ,  Srinivasan Ashok Anand ,  Srinivasan Parthasarathy ,  Yew Cheong Mui

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： C22C13/02 ,  B23K35/262 ,  H01L23/49811 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K3/3463 ,  H05K2201/10318 ,  H05K2201/10674 ,  H05K2203/047 ,  H01L2224/81 ,  H01L2224/0401

摘要： A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

摘要翻译： 封装衬底包括管芯焊盘和焊脚焊脚。 针焊料焊片可以包含约90重量％至约99重量％的锡和约10重量％至1重量％的锑。 模焊盘可以包括约4重量％至约8重量％的铋，约2重量％至约4重量％的银，约0重量％至约0.7重量％的铜，以及约87重量％至约92重量％ 锡。 模焊盘可以包括约7重量％至约20重量％的铟，约2重量％至约4.5重量％的银之间，约0重量％至约0.7重量％的铜之间，约0重量％至约0.5重量％ 重量锑，以及约74.3重量％至约90重量％的锡。

公开(公告)号：US06382500B1

公开(公告)日：2002-05-07

申请号：US09642835

申请日：2000-08-22

申请人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Sp Lee ,  Sofi Mohd

发明人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Sp Lee ,  Sofi Mohd

IPC分类号： B23K100

CPC分类号： B23K1/203 ,  B23K1/0016 ,  B23K1/008 ,  B23K2101/40

摘要： When soldering semiconductor devices in a solder reflow furnace flux is vaporized and carried to the furnace exhaust pipe. The flux condenses on the walls of the exhaust pipe and drips back into the furnace contaminating production parts. A solder reflow furnace with a flux effluent collector prevents flux drip-back. The flux effluent collector has an exhaust gas heater that maintains flux effluent in a gaseous state, a flux cooler, to subsequently condense flux, and a flux condensation region where the flux condenses. The flux condensation region is offset from the furnace's exhaust opening so that condensed flux cannot drip back into the furnace.

摘要翻译： 当在焊料回流炉中焊接半导体器件时，助熔剂被蒸发并运送到炉排气管。 助焊剂在排气管的壁上冷凝并滴入炉中，污染生产部件。 具有助焊剂流出物收集器的焊料回流炉防止焊剂滴落。 助焊剂流出物收集器具有一个废气加热器，其保持处于气态的助熔剂流出物，助熔剂冷却器，随后冷凝助熔剂，以及通量冷凝的助熔剂冷凝区域。 助熔剂冷凝区域与炉的排气口偏离，使得冷凝的通量不能滴入炉中。

公开(公告)号：US06333253B1

公开(公告)日：2001-12-25

申请号：US09696049

申请日：2000-10-26

申请人： Terri J. Brownfield ,  Raj N. Master

发明人： Terri J. Brownfield ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  B23K1/203 ,  B23K3/082 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/3489

摘要： A method and apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor by mounting a flux stamp on the semiconductor chip. The flux stamp has a plurality of flux holes arranged in a pattern substantially identically corresponding to the arrangement of the flip-chip bumps of the semiconductor chip. Different flux stamps are prepared for various kinds of semiconductor chips having different flip-chip bump arrangements. Flux is deposited though the flux holes of the flux stamp which selectively exposing the upper surfaces of the flip-chip bumps of the chip, thereby leaving no flux on the chip surface between the flip-chip bumps.

摘要翻译： 提供一种方法和装置，用于通过在半导体芯片上安装焊剂印模来选择性地在布置在半导体上的多个倒装凸块上沉积焊剂。 磁通印模具有以与半导体芯片的倒装芯片凸块的布置基本相同的形式布置的多个磁通孔。 为具有不同倒装芯片凸块布置的各种半导体芯片准备不同的磁通量戳。 焊剂通过焊剂压块的通孔沉积，其选择性地暴露芯片的倒装芯片凸块的上表面，从而在倒装芯片凸块之间的芯片表面上不留下焊剂。

公开(公告)号：US5988485A

公开(公告)日：1999-11-23

申请号：US40651

申请日：1998-03-17

申请人： Raj N. Master ,  Orion K. Starr ,  Mohammad Z. Khan

发明人： Raj N. Master ,  Orion K. Starr ,  Mohammad Z. Khan

IPC分类号： H01L21/60 ,  H01L21/48 ,  B23K1/018

CPC分类号： H01L21/4864 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701

摘要： A method of assembling a substrate and die in a flip chip configuration uses a non-hazardous cleaning solvent to clean the flux residue. The non-hazardous cleaning solvent utilized is Ionox obtained from Kyzen Corporation. Optimized process parameters are: time 10-30 minutes, temperature 70-90.degree. C., pressure 40-70 psi, rotation speed and reversals 100-1000 rpm and 24-100 reversal cycles.

摘要翻译： 以倒装芯片配置组装衬底和管芯的方法使用非危险清洁溶剂来清洁焊剂残留物。 使用的非危险清洗溶剂是从Kyzen Corporation获得的Ionox。 优化的工艺参数为：时间10-30分钟，温度70-90℃，压力40-70psi，转速和反转100-1000转和24-100反转循环。