公开(公告)号：US12066957B2

公开(公告)日：2024-08-20

申请号：US18130355

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1684 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/079 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1658 ,  G06F11/2007 ,  G06F13/4027 ,  Y02D10/00

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20240265953A1

公开(公告)日：2024-08-08

申请号：US18581694

申请日：2024-02-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US12026038B2

公开(公告)日：2024-07-02

申请号：US18449118

申请日：2023-08-14

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/00 ,  H04L1/08 ,  H04L1/1809

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/004 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US11990912B2

公开(公告)日：2024-05-21

申请号：US17883345

申请日：2022-08-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G06F13/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02

CPC classification number: H03K5/13 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G06F13/00 ,  G06F13/4243 ,  G11C7/04

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

公开(公告)号：US11967364B2

公开(公告)日：2024-04-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G06F11/10 ,  G11C7/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US11955198B2

公开(公告)日：2024-04-09

申请号：US18097459

申请日：2023-01-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US20240111625A1

公开(公告)日：2024-04-04

申请号：US18233250

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/10 ,  G06F11/16 ,  G11C7/10 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  H03M13/1575 ,  G06F11/20

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US20240078044A1

公开(公告)日：2024-03-07

申请号：US18371300

申请日：2023-09-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/4282

Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.

公开(公告)号：US20240062788A1

公开(公告)日：2024-02-22

申请号：US18373162

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C7/08 ,  G11C5/025 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US11900981B2

公开(公告)日：2024-02-13

申请号：US18078934

申请日：2022-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/00 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/00

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.