公开(公告)号：US10482962B2

公开(公告)日：2019-11-19

申请号：US15979669

申请日：2018-05-15

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

Inventor： Cheol Kim ,  Hyun-Suk Kang ,  Kee-Won Kwon ,  Rak-Joo Sung ,  Sung-Gi Ahn

IPC: G11C15/04 ,  G11C15/00 ,  G11C13/00

Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

公开(公告)号：US20190252540A1

公开(公告)日：2019-08-15

申请号：US16394671

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Kim ,  Kyung-Seok Oh ,  Cheol Kim ,  Heon-Jong Shin ,  Jong-Ryeol Yoo ,  Hyun-Jung Lee ,  Seong-Hoon Jeong

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US20170229192A1

公开(公告)日：2017-08-10

申请号：US15498855

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/42 ,  G11C11/4094 ,  G11C29/00 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C11/4096

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09704558B2

公开(公告)日：2017-07-11

申请号：US15224683

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-yeon Doo ,  Tae-young Oh ,  Cheol Kim ,  Geun-tae Park

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/40626 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4091

Abstract: Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.

公开(公告)号：US09190404B2

公开(公告)日：2015-11-17

申请号：US13949289

申请日：2013-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Sun Lee ,  Myeongcheol Kim ,  Cheol Kim ,  Sanghyun Lee

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L27/02 ,  H01L27/11 ,  H01L23/485

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/78 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode.

Abstract translation: 提供半导体器件及其制造方法。 器件可以包括在包括栅极绝缘图案，栅极电极和杂质区域的衬底上的晶体管，电连接到栅极电极和杂质区域的共用接触插塞以及栅极侧表面之间的蚀刻停止层 电极和共用触点。 共享接触插头可以包括电连接到第一杂质区域的第一导电图案和电连接到栅电极的第二导电图案，并且第一导电图案的顶表面可以高于栅电极的顶表面。

公开(公告)号：US12243754B2

公开(公告)日：2025-03-04

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young Choi ,  Sung Min Kim ,  Cheol Kim ,  Hyo Jin Kim ,  Dae Won Ha ,  Dong Woo Han

IPC: H01L21/3213 ,  H01L21/308 ,  H01L27/088 ,  H01L27/092

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US12148749B2

公开(公告)日：2024-11-19

申请号：US17502554

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a substrate, first and second active patterns, each including first and second side walls, a field insulation layer surrounding side walls of each of the first and second active patterns, a first dam between the first and second active patterns and having a lower surface lower than an upper surface of the field insulation layer, a second dam spaced apart from the first side wall of the first active pattern and having a lower surface lower than the upper surface of the field insulation layer, a first gate electrode on the first dam between the first and second active patterns, a second gate electrode spaced apart from the first gate electrode, and a first gate cut spaced apart from each of the first side walls of each of the first and second active patterns and intersecting each of the first and second gate electrodes.

公开(公告)号：US20240170358A1

公开(公告)日：2024-05-23

申请号：US18378603

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokgeun Ahn ,  Cheol Kim ,  Hwanyoung Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A semiconductor package includes a lower redistribution structure, a first semiconductor chip and a second semiconductor chip that stacked on the lower redistribution structure, the second semiconductor chip including a heat dissipation pad disposed at an upper surface of the second semiconductor chip, a lower conductive pillar disposed on the lower redistribution structure, an upper conductive pillar disposed on the lower conductive pillar, a heat dissipation pillar disposed on the heat dissipation pad, an upper redistribution structure disposed on the upper conductive pillar; and a heat dissipation structure disposed on the heat dissipation pillar.

公开(公告)号：US20220406775A1

公开(公告)日：2022-12-22

申请号：US17713834

申请日：2022-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Dongkwon Kim ,  Hyunho Jung

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have different side profiles.

公开(公告)号：US11271110B2

公开(公告)日：2022-03-08

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong Lee ,  Sanghyuk Hong ,  TaeYong Kwon ,  Sunjung Kim ,  Cheol Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.