公开(公告)号：US20170098652A1

公开(公告)日：2017-04-06

申请号：US15229424

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeol Kang ,  Ki-Vin Im ,  Youn-Soo Kim ,  Han-Jin Lim

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10805 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

Abstract: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

公开(公告)号：US09202844B2

公开(公告)日：2015-12-01

申请号：US13966423

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jong Han ,  Yoon-Goo Kang ,  Won-Seok Yoo ,  Kong-Soo Lee ,  Han-Jin Lim ,  Seong-Hoon Jeong

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

Abstract translation: 半导体器件包括在具有第一导电型杂质的衬底上的具有第二导电类型杂质的下互连。 开关装置在较低的互连上。 第一阻挡层设置在下互连和开关器件之间。 第一阻挡层包括碳（C），锗（Ge）或其组合。 第二阻挡层可以设置在基板和下部互连件之间。

公开(公告)号：US20140231958A1

公开(公告)日：2014-08-21

申请号：US14070988

申请日：2013-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Jin Lim ,  Seok-Woo Nam ,  Jung-Hwan Oh ,  Ki-Vin Im

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/1085

Abstract: A capacitor of a memory device includes dielectric layers with different energy band gaps. The capacitor may include, for example, a first electrode and a first dielectric layer on the first electrode. The capacitor may further include a second dielectric layer on the first dielectric layer. The first and second dielectric layers may include the same dielectric material with different concentration of an impurity therein. A second electrode is disposed on the second dielectric layer.

Abstract translation: 存储器件的电容器包括具有不同能带隙的电介质层。 电容器可以包括例如第一电极和第一电极上的第一电介质层。 电容器还可以包括在第一电介质层上的第二电介质层。 第一和第二电介质层可以包括具有不同浓度的杂质的相同介电材料。 第二电极设置在第二电介质层上。

公开(公告)号：US10685959B2

公开(公告)日：2020-06-16

申请号：US16220109

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Kak Lee ,  Joon Kim ,  Bong-hyun Kim ,  Han-Jin Lim

IPC: H01L21/311 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

公开(公告)号：US10403638B2

公开(公告)日：2019-09-03

申请号：US15610923

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Suk Lee ,  Hong-Suk Kim ,  Jae-Young Ahn ,  Han-Jin Lim

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11582

Abstract: A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

公开(公告)号：US09812557B2

公开(公告)日：2017-11-07

申请号：US15138234

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Dong-Suk Shin ,  Woon-Ki Shin ,  Cheol-Woo Park ,  Ryong Ha ,  Han-Jin Lim

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02068 ,  H01L21/32134 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.

公开(公告)号：US09716094B2

公开(公告)日：2017-07-25

申请号：US15229424

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeol Kang ,  Ki-Vin Im ,  Youn-Soo Kim ,  Han-Jin Lim

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10805 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

Abstract: A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

公开(公告)号：US09455259B2

公开(公告)日：2016-09-27

申请号：US14716371

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。

公开(公告)号：US20160079247A1

公开(公告)日：2016-03-17

申请号：US14716371

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。

公开(公告)号：US09230922B2

公开(公告)日：2016-01-05

申请号：US14180907

申请日：2014-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Jin Lim ,  Bong-Hyun Kim ,  Seok-Woo Nam ,  Dong-Woon Shin ,  In-Sang Jeon ,  Soo-Jin Hong

IPC: H01L21/31 ,  H01L23/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L23/564 ,  C23C16/402 ,  C23C16/45553 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28194 ,  H01L23/562 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): HxSiAy(NR1R2)4-x-y  (1) HxSi(NAR3)4-x  (2) HxSi(R4)z(R5)4-x-z  (3) wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R1, R2, R3, and R5 are each independently selected from the group of H, aryl, perhaloaryl, C1-8 alkyl, and C1-8 perhaloalkyl, and R4 is aryl in which at least one hydrogen is replaced with a halogen or C1-8 alkyl in which at least one hydrogen is replaced with a halogen.

Abstract translation: 一种用于在基底上形成二氧化硅膜的前体组合物，所述前体组合物包含至少一种由以下化学式（1），（2）和（3）表示的前体化合物：HxSiAy（NR1R2）4-xy（1 ）其中独立地在化学式（1），（2）和（3）中，H是氢，x，x，x，x，y， 为0〜3，Si为硅，A为卤素，y为1〜4，N为氮，R1，R2，R3，R5各自独立地选自H，芳基，全卤代芳基，C1-8 烷基和C 1-8全卤代烷基，R 4是其中至少一个氢被卤素取代的芳基或其中至少一个氢被卤素取代的C 1-8烷基。