公开(公告)号：US20180151589A1

公开(公告)日：2018-05-31

申请号：US15843659

申请日：2017-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Satoshi SHIMIZU ,  Hiroyuki OGAWA ,  Yasuo KASAGI ,  Kento KITAMURA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A layer stack including a lower semiconductor layer, a lower dielectric layer, and a spacer material layer is formed over a semiconductor substrate, and the spacer material layer is patterned to form spacer line structures. An upper dielectric layer and an upper semiconductor layer are formed, followed by formation of an alternating stack of insulating layers and spacer material layers. Memory stack structures are formed through the alternating stack, the upper semiconductor layer, and the dielectric material layer. The upper semiconductor layer, the upper dielectric layer, and the lower semiconductor layer can be patterned to form a buried source layer and at least one passive device. Each passive device can include a lower semiconductor plate, a dielectric material plate, and an upper semiconductor plate. Each passive device can be a resistor or a capacitor.

公开(公告)号：US20240206170A1

公开(公告)日：2024-06-20

申请号：US18352012

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20220254733A1

公开(公告)日：2022-08-11

申请号：US17174064

申请日：2021-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Genta MIZUNO ,  Kenzo IIZUKA ,  Satoshi SHIMIZU ,  Keisuke IZUMI ,  Tatsuya HINOUE ,  Yujin TERASAWA ,  Seiji SHIMABUKURO ,  Ryousuke ITOU ,  Yanli ZHANG ,  Johann ALSMEIER ,  Yusuke YOSHIDA

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

公开(公告)号：US20210036004A1

公开(公告)日：2021-02-04

申请号：US16583906

申请日：2019-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi MORIYAMA ,  Yasushi DOWAKI ,  Yuki KASAI ,  Satoshi SHIMIZU ,  Jayavel PACHAMUTHU

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

公开(公告)号：US20240292616A1

公开(公告)日：2024-08-29

申请号：US18357634

申请日：2023-07-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Shinsuke YADA ,  Satoshi SHIMIZU

IPC: H10B43/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes a source layer, an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer, and a source-control electrode located over the source-control-gate dielectric.

公开(公告)号：US20200343258A1

公开(公告)日：2020-10-29

申请号：US16394233

申请日：2019-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Satoshi SHIMIZU ,  Makoto KOTO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

公开(公告)号：US20180122906A1

公开(公告)日：2018-05-03

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Kento KITAMURA ,  Tong ZHANG ,  Chun GE ,  Yanli ZHANG ,  Satoshi SHIMIZU ,  Yasuo KASAGI ,  Hiroyuki OGAWA ,  Daxin MAO ,  Kensuke YAMAGUCHI ,  Johann ALSMEIER ,  James KAI

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.