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    THREE-DIMENSIONAL MEMORY ARRAY INCLUDING DUAL WORK FUNCTION FLOATING GATES AND METHOD OF MAKING THE SAME
    11.
    发明申请
    THREE-DIMENSIONAL MEMORY ARRAY INCLUDING DUAL WORK FUNCTION FLOATING GATES AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20220254798A1

    公开(公告)日：2022-08-11

    申请号：US17351720

    申请日：2021-06-18

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Ramy Nashed Bassely SAID ,  Yanli ZHANG ,  Jiahui YUAN ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA

    IPC: H01L27/11556 ,  H01L29/49

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTILEVEL DRAIN SELECT GATE ISOLATION AND METHODS OF MAKING THE SAME
    14.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTILEVEL DRAIN SELECT GATE ISOLATION AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200006358A1

    公开(公告)日：2020-01-02

    申请号：US16019856

    申请日：2018-06-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Masatoshi NISHIKAWA ,  Shinsuke YADA ,  Yanli ZHANG

    IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

    FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME
    18.
    发明申请
    FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20230082824A1

    公开(公告)日：2023-03-16

    申请号：US17562635

    申请日：2021-12-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Srinivas PULUGURTHA ,  Yanli ZHANG ,  Johann ALSMEIER ,  Mitsuhiro TOGO

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

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