公开(公告)号：US20150054140A1

公开(公告)日：2015-02-26

申请号：US14519832

申请日：2014-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/538 ,  H01L25/07 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract translation: 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 壳体通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US08907481B2

公开(公告)日：2014-12-09

申请号：US13869072

申请日：2013-04-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract translation: 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 外壳通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US10403682B2

公开(公告)日：2019-09-03

申请号：US15968474

申请日：2018-05-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Morin ,  Philippe Brun ,  Laurent-Luc Chapelon

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

公开(公告)号：US09136233B2

公开(公告)日：2015-09-15

申请号：US14293341

申请日：2014-06-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L29/06 ,  H01L21/30 ,  H01L23/00 ,  H01L23/427 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region.

Abstract translation: 三维集成结构包括具有与具有基板的第二集成电路以互锁方式组装的基板的第一集成电路。 第一集成电路的衬底包括由第一隔板分开的第一孔，并且第二集成电路的衬底包括由第二隔板分开的第二孔。 与第二孔互锁的第一隔板和第二隔板与第一孔互锁，以限定由两个基板界定的至少一个区域。 相变材料保留在至少一个区域内。

公开(公告)号：US08896121B2

公开(公告)日：2014-11-25

申请号：US13765760

申请日：2013-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/492 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/4924 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80097 ,  H01L2224/80357 ,  H01L2225/06513 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/05042 ,  H01L2924/04642 ,  H01L2924/059 ,  H01L2924/049

Abstract: An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.

Abstract translation: 半导体晶片/芯片的组件，其中两个晶片/芯片的相邻表面包括其中插入有相对的铜焊盘的绝缘层。 绝缘层由选自包括氮化硅和氮化碳的组的材料制成。

公开(公告)号：US20130207279A1

公开(公告)日：2013-08-15

申请号：US13766925

申请日：2013-02-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mohamed BOUCHOUCHA ,  Laurent-Luc Chapelon

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/16146 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method for forming an integrated circuit including the steps of: forming electronic capponents on a first surface of a substrate; forming a stack of interconnection levels on the first surface, each interconnection level including conductive tracks separated by an insulating material; forming at least one hole from a second surface of the substrate, opposite to the first surface, the hole stopping on one of the conductive tracks; depositing, on the walls and the bottom of the hole, a conductive layer and filling the remaining space with a filling material; and forming, in an interconnection level or at the surface of the interconnection stack, and opposite to said at least one hole, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, insulated from the conductive tracks.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：在基板的第一表面上形成电子支撑件; 在所述第一表面上形成一叠互连层，每个互连层包括由绝缘材料隔开的导电轨道; 从所述基板的与所述第一表面相对的第二表面形成至少一个孔，所述孔在所述导电轨道中的一个上停止; 在孔的壁和底部上沉积导电层并用填充材料填充剩余的空间; 以及在所述互连叠层的互连层或所述表面上形成并与所述至少一个孔相对的材料的至少一个区域，其弹性模量大于50GPa，断裂伸长率大于20％ ，与导电轨道绝缘。

公开(公告)号：US09455239B2

公开(公告)日：2016-09-27

申请号：US14743072

申请日：2015-06-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon ,  Julien Cuzzocrea

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13657 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

公开(公告)号：US09093456B2

公开(公告)日：2015-07-28

申请号：US14519832

申请日：2014-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L25/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract translation: 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 壳体通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US20140361413A1

公开(公告)日：2014-12-11

申请号：US14293341

申请日：2014-06-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/373 ,  H01L23/00

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region.

Abstract translation: 三维集成结构包括具有与具有基板的第二集成电路以互锁方式组装的基板的第一集成电路。 第一集成电路的衬底包括由第一隔板分开的第一孔，并且第二集成电路的衬底包括由第二隔板分开的第二孔。 与第二孔互锁的第一隔板和第二隔板与第一孔互锁，以限定由两个基板界定的至少一个区域。 相变材料保留在至少一个区域内。

公开(公告)号：US08890276B2

公开(公告)日：2014-11-18

申请号：US13934683

申请日：2013-07-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L31/058 ,  H01L27/04 ,  H01L21/66 ,  G01K5/56 ,  H01L23/00

CPC classification number: H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

Abstract translation: 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。