公开(公告)号：US20170345822A1

公开(公告)日：2017-11-30

申请号：US15676317

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kee Sang Kwon ,  Boun YOON ,  Sangjine PARK ,  Myunggeun SONG ,  Ki-Hyung KO ,  Jiwon YUN

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49

Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US20170207130A1

公开(公告)日：2017-07-20

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung PARK ,  Ju-Hyun KIM ,  Hoyoung KIM ,  Boun YOON ,  TaeYong KWON ,  Sangkyun KIM ,  Sanghyun PARK

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L21/3105

CPC classification number: H01L21/823807 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US20140227848A1

公开(公告)日：2014-08-14

申请号：US14146185

申请日：2014-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo Kyeong KANG ,  Jaeseok KIM ,  Boun YOON ,  Hoyoung KIM ,  Ilyoung YOON

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽，并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

公开(公告)号：US20230332015A1

公开(公告)日：2023-10-19

申请号：US18096231

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inkwon KIM ,  Yearin Byun ,  Sangkyun KIM ,  Boun YOON ,  Hyosan LEE

IPC: H01L21/768 ,  C09G1/02 ,  C09G1/04 ,  H01L21/321

CPC classification number: C09G1/02 ,  C09G1/04 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843

Abstract: A slurry composition for polishing metal and a method of manufacturing an integrated circuit device, the slurry composition includes a first organic polishing booster including a cationic polymer salt that includes a quaternary ammonium cation; a second organic polishing booster including an organic acid; an oxidizer; a pH adjuster; 0 wt% to about 0.1 wt% of an inorganic abrasive; and water.

公开(公告)号：US20230328986A1

公开(公告)日：2023-10-12

申请号：US18070536

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Chungki MIN ,  Boun YOON ,  Kihoon JANG

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556

Abstract: A semiconductor device includes a source structure, first and second stack structures, including first gate electrodes stacked on the source structure to be spaced apart from each other; a dummy structure on the source structure between the first and the second stack structures, and including second gate electrodes stacked to be spaced apart from each other; first separation regions passing through the first and second stack structures, and spaced apart from each other; second separation regions extending between each of the first and second stack structures and the dummy structure; channel structures passing through the first and second stack structures, and respectively including a channel layer, connected to the source structure through the channel layer; and first source contact structures passing through the dummy structure, and respectively including a first contact layer connected to the source structure through a lower surface of the first contact layer.

公开(公告)号：US20190157279A1

公开(公告)日：2019-05-23

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom PYON ,  Kichul PARK ,  Inkwon KIM ,  Ki Hoon JANG ,  Byoungho KWON ,  Sangkyun KIM ,  Boun YOON

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L27/11286 ,  H01L21/02107 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US20170301773A1

公开(公告)日：2017-10-19

申请号：US15632735

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine PARK ,  Jae-Jik BAEK ,  Myunggeun SONG ,  Boun YOON ,  Sukhun CHOI ,  Jeongnam HAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

公开(公告)号：US20240100647A1

公开(公告)日：2024-03-28

申请号：US18127382

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Boun YOON

IPC: B24B37/20

CPC classification number: B24B37/205

Abstract: A substrate processing apparatus includes a substrate support portion including a platen and a transparent polishing pad on the platen, the platen comprising a light generator that generates light that passes through the transparent polishing pad and proceeds towards a semiconductor substrate on the substrate support portion, and the transparent polishing pad including a surface that contacts and polishes the semiconductor substrate. The substrate processing apparatus further includes: a substrate holder that fixes the semiconductor substrate such that the semiconductor substrate is in contact with the substrate support portion; and a slurry supply portion that supplies slurry between the semiconductor substrate and the transparent polishing pad. The slurry includes a light blocking material that blocks the light; and abrasive particles that are configured to be activated by accepting electrons generated, based on the light, by a photocatalyst within the slurry.

公开(公告)号：US20230422501A1

公开(公告)日：2023-12-28

申请号：US18190876

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Beomjin PARK ,  Boun YOON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.

公开(公告)号：US20230328987A1

公开(公告)日：2023-10-12

申请号：US18150415

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Boun YOON ,  Kihoon JANG

IPC: H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L23/528 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes gate electrodes stacked on the second substrate, interlayer insulating layers alternately stacked with the gate electrodes, through-insulating regions passing through the gate electrodes in a second region, a capping insulating layer covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer, channel structures passing through the capping insulating layer and the gate electrodes in a first region, upper contact plugs passing through the upper insulating layer, bit lines on the upper insulating layer, first contact plugs passing through the capping insulating layer, and conductive patterns including second contact plugs passing through each of the through-insulating regions in the second region. The conductive patterns include connection portions integral with the second contact plugs.