Abstract:
There is provided a semiconductor light-emitting device including a base layer formed of a first conductivity-type semiconductor material, and a plurality of light-emitting nanostructures disposed on the base layer to be spaced apart from each other, and including first conductivity-type semiconductor cores, active layers, and second conductivity-type semiconductor layers. The first conductivity-type semiconductor cores include rod layers extending upwardly from the base layer, and capping layers disposed on the rod layers. Heights of the rod layers are different in at least a portion of the plurality of light-emitting nanostructures, and heights of the capping layers are different in at least a portion of the plurality of light-emitting nanostructures.
Abstract:
A nanostructure semiconductor light emitting device may include a substrate including a plurality of light emitting nanostructures comprising nanocores including a first conductivity type semiconductor, active layers and second conductivity type semiconductor layers sequentially formed on the nanocores. The light emitting region may include a first region and a second region. The interval between the light emitting nanostructures disposed in the first region may be different than the interval between the light emitting nanostructures disposed in the second region. The first region may be closer to a non-light emitting region than the second region and may have a smaller interval between the light emitting nanostructures than that of the second region. Systems implementing such a nanostructure semiconductor light emitting device and methods of manufacture are also disclosed.
Abstract:
A method of manufacturing a display module includes preparing a first substrate structure including an light-emitting diode (LED) array containing a plurality of LED cells, electrode pads connected to the first and second conductivity-type semiconductor layers, and a first bonding layer covering the LED array; preparing a second substrate structure including a plurality of thin-film transistor (TFT) cells disposed on a second substrate, and each having a source region, a drain region and a gate electrode disposed therebetween, the second substrate structure being provided by forming a circuit region, in which connection portions disposed to correspond to the electrode pads are exposed to one surface thereof, and by forming a second bonding layer covering the circuit region, respectively planarizing the first and second bonding layers, and bonding the first and second substrate structures to each other.
Abstract:
A chip mounting method includes providing a first substrate including a light transmissive substrate having first and second surfaces, a sacrificial layer provided on the first surface, and a plurality of chips bonded to the sacrificial layer, obtaining first mapping data by testing the chips, the first mapping data defining coordinates of normal chips and defective chips among the chips, disposing a second substrate below the first surface, disposing the normal chips on the second substrate by radiating a first laser beam to positions of the sacrificial layer corresponding to the coordinates of the normal chips, based on the first mapping data, to remove portions of the sacrificial layer thereby separating the normal chips from the light transmissive substrate, and mounting the normal chips on the second substrate by radiating a second laser beam to a solder layer of the second substrate.
Abstract:
A light emitting device package includes a first wavelength conversion portion and a second wavelength conversion portion to provide a wavelength of incident light to provide light having a converted wavelength, a light-transmissive partition structure extending along side surfaces of the first and second wavelength conversion portions along a thickness direction to separate the first and second wavelength conversion portions part from each other along a direction crossing the thickness direction, and a cell array including a first light emitting device, a second light emitting device and a third light emitting device, overlapping the first wavelength conversion portion, the second wavelength conversion portion and the light-transmissive partition structure, respectively, along the thickness direction.
Abstract:
A light emitting device package including a cell array including first, second and third light emitting devices each including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, the cell array having a first surface and a second surface opposing the first surface, a light-transmissive substrate including a first wavelength conversion portion and a second wavelength conversion portion corresponding to the first light emitting device and the second light emitting device, respectively, and bonded to the first surface, and a eutectic bonding layer including a first light emitting window, a second light emitting window and a third light emitting window corresponding to the first light emitting device, the second light emitting device and the third light emitting device, respectively, and bonding the light-transmissive substrate and the first to third light emitting devices to each other may be provided.
Abstract:
There is provided a semiconductor light emitting device including a first conductivity-type semiconductor base layer and a plurality of light emitting nanostructures disposed to be spaced apart from one another on the first conductivity-type semiconductor base layer, each light emitting nanostructure including a first conductivity-type semiconductor core, an active layer, an electric charge blocking layer, and a second conductivity-type semiconductor layer, respectively, wherein the first conductivity-type semiconductor core has different first and second crystal planes in crystallographic directions.
Abstract:
A method for manufacturing a semiconductor light emitting device may include steps of forming a mask layer and a mold layer having a plurality of openings exposing portions of a base layer, forming a plurality of first conductivity-type semiconductor cores each including a body portion extending through each of the openings from the base layer and a tip portion disposed on the body portion and having a conical shape, and forming an active layer and a second conductivity-type semiconductor layer on each of the plurality of first conductivity-type semiconductor cores. The step of forming the plurality of first conductivity-type semiconductor cores may include forming a first region such that a vertex of the tip portion is positioned on a central vertical axis of the body portion, removing the mold layer, and forming an additional growth region on the first region such that the body portion has a hexagonal prism shape.
Abstract:
A semiconductor light emitting device including a first conductive semiconductor base layer on a substrate; an insulating layer on the first conductive semiconductor base layer, the insulating layer including a plurality of openings through which the first conductive semiconductor base layer is exposed; and a plurality of nanoscale light emitting structures on the first conductive semiconductor base layer, the nanoscale light emitting structures respectively including a first conductive semiconductor core on an exposed region of the first conductive semiconductor base layer, and an active layer, and a second conductive semiconductor layer sequentially disposed on a surface of the first conductive semiconductor core, wherein a lower edge of a side portion of each nanoscale light emitting structure is on an inner side wall of the opening in the insulating layer.
Abstract:
There is provided a semiconductor light emitting device including a first conductivity-type semiconductor base layer and a plurality of light emitting nanostructures disposed to be spaced apart from one another on the first conductivity-type semiconductor base layer, each light emitting nanostructure including a first conductivity-type semiconductor core, an active layer, an electric charge blocking layer, and a second conductivity-type semiconductor layer, respectively, wherein the first conductivity-type semiconductor core has different first and second crystal planes in crystallographic directions.