公开(公告)号：US11721673B2

公开(公告)日：2023-08-08

申请号：US17568558

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuekjae Lee ,  Jihoon Kim ,  Jihwan Suh ,  Soyoun Lee ,  Jiseok Hong ,  Taehun Kim ,  Jihwan Hwang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/16 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/16 ,  H01L23/31 ,  H01L23/5386 ,  H01L24/14

Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.

公开(公告)号：US20230076511A1

公开(公告)日：2023-03-09

申请号：US18054530

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US11289438B2

公开(公告)日：2022-03-29

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US12237308B2

公开(公告)日：2025-02-25

申请号：US18400497

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-Woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US20240234374A9

公开(公告)日：2024-07-11

申请号：US18400497

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-Woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US11984421B2

公开(公告)日：2024-05-14

申请号：US17228111

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Song ,  Hongjoo Baek ,  Kyungsuk Oh ,  Manho Lee ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L24/24 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5286 ,  H01L2224/24265 ,  H01L2924/19041

Abstract: An integrated circuit chip includes a substrate having an active surface and a back surface opposite to the active surface; a front-end-of-line (FEOL) structure disposed on the active surface of the substrate; a first back-end-of-line (BEOL) structure disposed on the FEOL structure; an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer including a charge storage, and metal posts disposed around the charge storage; and a re-distribution structure layer disposed under the intermediate connection layer.

公开(公告)号：US20240055372A1

公开(公告)日：2024-02-15

申请号：US18315689

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Jihoon Kim ,  Seungduk Baek ,  Hyuekjae Lee

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1438 ,  H01L2224/94 ,  H01L2224/80895

Abstract: A semiconductor device includes a substrate and a lower die on the substrate. The lower die includes a first semiconductor substrate having a first device region and a first edge region therein, a first semiconductor element on the first device region, a first pad on the first device region and on the first semiconductor element, and a first interconnection structure connecting the first semiconductor element to the first pad. The first interconnection structure includes a first signal pattern on the first device region and connected to the first semiconductor element, a second signal pattern on the first device region and directly connected to the first pad, and a first dummy pattern at the same level as the second signal pattern and disposed on the first edge region. An upper die is provided, which is bonded to the lower die such that the first pad of the lower die is in contact with a second pad of the upper die.

公开(公告)号：US11901336B2

公开(公告)日：2024-02-13

申请号：US17355874

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US20230163088A1

公开(公告)日：2023-05-25

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/06 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L21/561 ,  H01L25/50 ,  H01L24/94 ,  H01L24/96 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/83099 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2224/32145 ,  H01L2224/08148 ,  H01L2224/08145 ,  H01L2224/05073 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/05562 ,  H01L2224/08121 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/08225 ,  H01L2224/32225 ,  H01L2224/92142 ,  H01L2224/8389 ,  H01L2224/80895

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11658148B2

公开(公告)日：2023-05-23

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jihoon Kim ,  JiHwan Suh ,  So Youn Lee ,  Jihwan Hwang ,  Taehun Kim ,  Ji-Seok Hong

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.